Hacker News Reader

Comment by no_time | Hacker News Reader

next up: custom FizzBuzz ASIC with 128 fizz and 128 buzz cores for maximum throughput.

Substandard design. You should have a suitable ratio of cores to keep them load balanced. I suggest 160 fizz cores and 96 buzz cores.

EDIT: And a fizzbuzz co-processor, obviously.

> fizzbuzz co-processor, obviously

One of the functional modules on the M1 Pro Max chip, but only the Max one, unfortunately.

Take that, Intel!

Or if your ASIC generalizes the problem in a slightly different direction, you end up reinventing TWINKLE and TWIRL: https://en.wikipedia.org/wiki/TWINKLE

Thanks for sharing this, its always amazing to see how physical properties can be used in weird ways to bypass normal "rules" of computation.

Could probably store all multiples of 3 and 5 up to some really big number burned directly to hardware and then do something like a big CAM table the way Internet core routers do mapping the numbers to ASCII bit strings. Then speedup IO by not having a general purpose display, but something more like an old-school digital clock that can only show digits and the words "fizz" and "buzz."

You'll get docked points from the typography nerd for displaying "fizz" instead of "ﬁzz"

That's definitely not going to be useful. By doing this 15 numbers at a time you completely avoid needing to do any division anyway. print FB, i+1. i+2, Fizz, i+3, Buzz. i+4, ... i+14. Then increment by 15.

Also, even with a very slow CPU you'd already run faster than can be perceived on a digital clock

I think optimizing binary tree inversion is a higher priority, right now.

Not for fizzbuzz optimisation it isn't! Get your priorities straight mate! Who is trying to get hired when we could be outputting more fizzes and/or buzzes! :)

FizzBuzzCoin?

Ah yes, the new junior developer technical interview

That would be easier.

Reply on news.ycombinator.com