Pre-decode lengths or stop-bits and more recently micro-op caches have been techniques that x86 has used to mitigate this and improve front end widths, for example.
People like Jim Keller (who has actually worked and lead teams implementing these very processors at Apple, Intel, and AMD!) basically say as much (while acknowledging decode is a little harder, in the large scheme of things on modern large cores it's not such a big deal):
https://chipsandcheese.com/2021/07/13/arm-or-x86-isa-doesnt-...
Andy Glew, one of the architects for Intel's first out of order x86 core (P6) among other things, is another who has said similar.
https://groups.google.com/g/comp.arch/c/elke1FHfYr0/m/SwW9NT...