There's few open source tools for any HDL full stop.

Indeed I'd say SystemVerilog is doing better on that front, as Verilator (https://www.veripool.org/verilator/) supports SystemVerilog and is probably the best open source tool for 'real' HDL work (note the number of industrial users).

I didn't mean open source, no, and it looks like the free version of yosys has limited support of systemverilog.

What I meant were the free toolchains provided by all of the FPGA vendors. They typically support SystemVerilog in synthesis and modelsim as far as I have seen.