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Comment by mtoner23 | Hacker News Reader

Fundementally? Bold claim

Verilog is weakly typed and VHDL is strong. That is already a pretty big deal when dealing with vector signals, where Verilog happily assigns a 32-bit signal to a 16-bit signal.

VHDL also supports defining record types, such that a collection of signals can be assigned together.

SystemVerilog also supports composite types using interfaces. Using Verilator as a linter will aggressively warn you about signal width mismatches.

Most complaints about Verilog from VHDL people come from outdated notions of the current state of the language and its tooling.

I also have a post on Verilog Lint with Verilator: https://projectf.io/posts/verilog-lint-with-verilator/

VHDLs type system is pretty rock solid it’s based off Ada after all. Which if you have looked at in any detail its a great type system!

I dont like the begin end style syntax and some the verbosity that entails with VHDL. However, I would rather create designs in VHDL than verilog when given the choice.

I come from a VHDL background (the industry I work in is purely VHDL), but recently I've been enjoying Systemverilog in my personal projects and it fixes a lot of these issues!

You can even do:

  typedef enum bit[1:0] {

    my_one, my_two, my_three, my_four

  } my_enum;

  typedef struct packed {

    my_enum b,

    bit [3:0] x

  } my_struct

  my_struct.b <= my_three;

etc...

It's been a nice path since I last dealt with Verilog. The concept of interfaces makes struct/vector input/output even nicer.

It's true that SystemVerilog fixed a lot of Verilog's deficiencies and took it more in the direction of VHDL. But a lot of free tools don't support SystemVerilog.

Hm, every vendor with free tools (Xilinx/Altera/Lattice/Microsemi etc), seem to be fine with it, along with the usual vendor-specific Modelsim. In fact, most "verilog" synthesis tools actually synthesize SystemVerilog. Out of curiosity what tool are you referring to?

Thanks!

There isn't much support if any in open source tools, if free means free software.

I didn't mean open source, no, and it looks like the free version of yosys has limited support of systemverilog.

What I meant were the free toolchains provided by all of the FPGA vendors. They typically support SystemVerilog in synthesis and modelsim as far as I have seen.

There's few open source tools for any HDL full stop.

Indeed I'd say SystemVerilog is doing better on that front, as Verilator (https://www.veripool.org/verilator/) supports SystemVerilog and is probably the best open source tool for 'real' HDL work (note the number of industrial users).

I don't know much about VHDL but Verilog (and SystemVerilog) are definitely fundamentally insane languages.

Any time VHDL comes up it's usually in the context of "this isn't a problem in VHDL". (But also "this would be way more verbose in VHDL")

One nice feature of VHDL we could use in modern software is different styles of descriptions of the same object in the same model: behavioral, structural, dataflow. The model can be given to tools operating at different levels: synthesis, simulation, verification etc.

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