Samsung Foundry Forum announcements

I want to add some context for those who dont follow Semi closely.

Samsung Foundry have a history of over promise and under deliver. This 3nm launch will likely be similar to their EUV node which they claim to be industry first but wasn't shipping in any real volume. So arguably they are not lying, but it is a marketing spin.

TSMC is an extremely pragmatic company. It either work or it doesn't, there is no need to save faces. No need to push industry first GAA or FinFET, push for whatever it works within the timeframe with respect to yield and cost. What is the point of having the best tech in 2022 when they cant produce it with enough volume that any of their customer would want?

That is not to say Samsung Foundry are evil or anything, they are pushing very very hard to try and catch up to TSMC and stays competitive in the market. ( Look at what happen to Global Foundry ). And now Intel is coming. Pat Gelsinger seems to be doing all the right thing.

Intel's switch to FinFET was equivalent to almost 2 node jumps. If they nail GAA, then it will probably be much better, but it will also be enormously more expensive to produce the chips.

Intel has loads of cash and would pay that money in a second, but I suspect that most other companies would rather hold off a bit longer in exchange for much cheaper products.

> I believe GAA is the next gen tech for the node process. Samsung is the first foundry to do GAA w/3nm while TSMC is sticking w/FinFET for their 3nm. It'll be interesting to see how 3nm FinFET compare to 3nm GAA.

Comparing Apples to Oranges, and doing doing a comparison on taste vs. size.

The device may well be awesome, but first ICs using it not so.

The biggest advancements in under 14nm were in metal, not so much with the device, process, or materials.

Even if Samsung will produce a better device design, they will still have to catch up to TSMC in so many, many other areas.

Only single digit number of people on this planet will ever know the exact measurements of FinFet vs. GAAFet

But one thing for sure, Samsung saying that they pioneered a new device ahead of TSMC does indeed sound very, and impressive to a certain category big co. people regardless of actual performance.

Their high-end phones have such dark patterns that I will flat-out not buy Samsung anything.

Even if you pay [€$]1000+ for one of their Smart Phones, you can look forward to:

* Uninstallable cruft, as if they were a telcom and you were on a contract and had not just handed over a grand

* ...like a confusingly-similar-looking competitor to Google Contacts that will upload your info to their servers

* GDPR? LOL

* A hard button on the side of your phone located just below the "volume down" button, easy to press accidentally, that is hard-coded and unconfigurable, that will launch their AI assistant Bixby. Don't want to use Bixby? Tough shit. Nothing you can do about it.

* Constant badgering by the phone's native notification to sign up for "Samsung Members", a social media platform. No, you can't turn that off.

* Other, similar bullshit.

3nm? These are such sketchy practices I cannot imagine it won't affect, say, their high-end TVs (they would totally monitor your house and show you advertisements).

Seriously, avoid that company. No, paying for their high-end options will not insulate you from their nonsense.

> 3nm is not actually 3nm

It's a stretch to blame that on Samsung, processor generations described in nanometres haven't been based on actual component size for years now, by any manufacturer.

I agree calling their display tech QLED is pretty shady, and clearly just intended to confuse people. But I'm glad their high end display tech is not OLED yet, because nobody seems to have solved burn in satisfactorily yet (if you play a lot of games or use them with a PC).

What is the best metric nowadays? Dhrystones/MIPS/FLOPS per MHz/Watt per square inch? As a complete outsider, millions of transistors per square inch sounds like a very intuitive metric of how small things are.

> 3nm is not actually 3nm

To be fair, I read the Xnm labelling is pretty much pure marketing at this point - since 45nm; https://en.wikichip.org/wiki/technology_node#Meaning_lost

And cpus are just sand

3nm means the process is equivalent in density and performance to a 3nm planar transistor that Samsung designed. I don't see how that is dishonorable marketing because every company designed their own reference planar transistors.

I thought the Q stood for quantum dot, which they actually use? (Not that that makes them unique nowadays).

> I'm fed up

Cool. I'm excited to get another Samsung phone. Suit yourself.

It should be ahead of Intel 4 ("4nm"). Samsung 5nm density is approximately 127M gates/mmsq on paper. Samsung 4nm will scale to around 0.75x area according to their China conference earlier this year, to a transistor density of around 168M gates/mmsq. They had another conference the other day detailing 3nm, which will scale down another 25%, to around 224M gates/mmsq.

Intel 4 was estimated to be up to 200M gates/mmsq. I don't think we have exact numbers since Intel only released numbers for their previous 10nm plan, which were heavily revised for Tigerlake iirc. I think Intel 3 is a variant of Intel 4 so 3GAA will presumably be similar to Intel 3.

edit: slides of the 3nm conference yesterday https://twitter.com/stshank/status/1445924295121592321/photo...

Intel actually renamed their nodes in like with Samsung and TSMC, so Intel 7 (used to called 10nm) is roughly comparable to TSMCs 7nm and Samsungs 8nm

It doesn’t relate to any measurement of feature size. It’s just a frustratingly meaningless marketing term.

>I can never remember what xnm means as it varies between companies.

Intel has renamed their node so the industry has now pretty much standardise on naming. Where all 3nm from Samsung, TSMC and Intel will have similar transistor density. ( But not similar performance or any other characteristic )

Officially Intel doesn't use 4nm or 3nm, they call it Intel 4 or Intel 3. But for the sake of easier comparison most people still use Intel 4nm to describe it.

There is also a big difference between the nm accuracy of lithography and the transistor size.

Creating chips with an accuracy of 1nm does not mean 1nm transistors.

But 1nm sounds good as marketing.

Well, I hope nobody chooses a fab based on the headline number on their marketing material. Adapting your design to them is a long process that requires all kinds of details, and how well they will produce your circuit depends on those details as much as on the feature size.

There’s not really a standard, some feature is probably 3nm, which feature chosen has varied over time and between companies.

Everyone is making excuses, but the simple answer is: yes, it’s misleading and deceptive.

It’s allowed, as many, many, many other bad things in this world are.

It's not supposed to be deceptive because the idea is that, say, the 3LPE process provides the same performance as an ideal classic 3 nm transistor.

3 nm is not the size of these transistors, just like X nm has never been the size of transistors for any value of X, so it's not "misleading and deceptive".

Actually it is all about marketing now, the customers though to whom they market are MNCs with immense cash piles to splurge on microchips. Nobody else can.

See — you rarely ever see so much marketing money spent on an industrial service, and like here seeing Hollywood level gfx on an obscure industry event keynote would've been more laughable than noteworthy 10 years ago.

Without these cash piles, there is no way to finance new fabs, and SEL is fighting for its survival here. Once you are out of the race in semi industry, you can never catch up.

First though, "5nm", "3nm" and so on are just marketing names. There is nothing about "5nm" that makes it "5nm" other than the company in question saying it is. Some things are smaller than 5nm on a given 5nm node, and some are larger. I cannot recall exactly what node this started to be the case (there used to be an actual definition, one for DRAM, one for logic), but it was in the past two decades and got particularly ridiculous beginning around "28nm" up to now. The really concerning physical dimension for quantum tunneling to occur/not occur is "gate length," and that's been basically sitting around ~16nm (actual, real, literal 16nm), plus or minus a few nanometers (depending on the manufacturer and process in question), since about "45nm" (mid-late 2000s). So that one critical dimension isn't getting smaller. And there isn't much they can do about it right now. They are still shrinking other dimensions though, and things don't work like they used to. Powered off transistors aren't really off, and leak power. The workaround for this is that they just use bigger transistors in certain places for what's called "power gating". You get the benefits of having tons of small transistors, with a slight area penalty. In addition to power gating, they have made substantial improvements to the design of the transistors themselves. Gates now wrap around the channel on 3 sides, creating a device known as a Finfet. Silicon dioxide is no longer used as an insulator to the same extent -- hafnium dioxide preforms much better as an insulator. Gates are now metal instead of polysilicon. And there's an assortment of other changes that have occurred or are on the way. So performance has actually managed to improve somewhat, and things have still gotten smaller. The end is near... but not quite yet. Gate length is not going to budge much unless some miracle occurs, though.

Quantum tunnelling has already become a problem in most computer components. NAND flash was the first in maybe 2015 to start reporting seeing issues?

Effects are moderately visible and have to be counteracted at 5nm. I heard some rumours about 7nm, but cannot confirm any countermeasures were taken to avoid quantum effects.

It should be noted that "3nm" is now purely for commercial reasons and has no relationship to the size of transistors on board.

It already has been a problem in terms of gate leakage, although largely mitigated by material improvements.

Gate leakage is the phenomenon of quantum tunneling through the gate dielectric barrier and started appearing as gate dielectrics became thinner and thinner. Gate leakage was mitigated by moving to higher k dielectrics (from silicon dioxide, SiO2, to more exotic materials that include other elements such as Hafnium).

Higher k dielectrics allow for the same capacitance per unit area and channel control with a thicker physical gate compared to plain SiO2, reducing gate leakage. This technology change came along with metal gates (which used to be polysilicon) and were a combined advance that Intel incorporated a few years before before TSMC, IIRC circa 2008.

This is a circuit designer's perspective. Someone who actually understands device physics and material properties can chime in to correct me.

It's always been a problem to some degree. Keep in mind that 3nm is a misnomer and has no real physical meaning behind it.

From a few years ago until we perfect the QFET and can put it to use.

With the old-school plane transistors over the wafer's silicon design, you need about 10nm of doped material so it won't completely mix with everything else.

With theoretical organic 1-electron designs you can build a transistor out of 4 carbon atoms. But nobody knows how to mass produce those ones.

We are somewhere on the middle, modern designs did break the 10nm barrier, but are not nearly as small as those numbers you see around.

The actual feature sizes are still (remember these shapes are 3D) quite a few scalings away from being even close to atoms.

3nm is a marketing term.