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Comment by Ericson2314 | Hacker News Reader

This is a misleading headline. It's a little FPGA program that's implemented 1990 style.

Just like Nios II, it's a processor. It doesn't have to be "hard" silicon. Calling it a "little FPGA program" seems very dismissive. I don't know what you mean by "1990 style".

> I don't know what you mean by "1990 style".

They said "5 stage", which sounds to me like no out-of-order fancy stuff of the sort we've been used to.

> Calling it a "little FPGA program" seems very dismissive.

Well, I wrote a little 5 stage CPU FPGA program once (In Haskell compiled to Verilog :), but that's another story). It wasn't very hard.

I haven't made a production IC, but I'm told that's much harder. I would be awesome if Intel made a RISC-V chip, even a slow one just good for arduino-type toys, but that's not what happened here.

> They said "5 stage", which sounds to me like no out-of-order fancy stuff of the sort we've been used to.

There's a lot of processors out there. The vast, vast majority being shipped are in order and a handful of stages.

> Well, I wrote a little 5 stage CPU FPGA program once (In Haskell compiled to Verilog :), but that's another story). It wasn't very hard.

> I haven't made a production IC, but I'm told that's much harder. I would be awesome if Intel made a RISC-V chip, even a slow one just good for arduino-type toys, but that's not what happened here.

The FPGA vendor provided soft cores have about the same amount of engineering rigor as a hard core. They have enough customers for the designs to have enough reach to have the same financial implications for bugs.

   The FPGA vendor provided soft cores have about the same amount of engineering rigor as a hard core.

I'm not sure what you mean by engineering rigor, but there is indeed plenty of engineering to get from a soft core to a hard core, let alone a fabricated, working chip: synthesis, layout, place and route, timing closure, pads, PLL/DLL, clock tree insertion, BIST, thermal, packaging, etc...

High end soft cores do most of that. Particularly when you consider that most of what isn't automated these days is equally applicable to soft cores that aren't just Verilog or VHDl. Floor planning FPGA cores these days can be nutty compared to the recent past (far past interestingly enough was similar before you had higher level tools). And the fact that stuff like packaging, DLLs/PLLs are equally applicable to hard cores. That's outside of what they care about on nearly every core design I've seen (albeit I'm only in my mid 30s).

>arduino-type toys

Intel has a terrible track record with maker-ish stuff. They routinely launch products, sell them for a year, then discontinue them. (Intel Euclid vision SBC, Intel Edison x86 microcontroller, the realsense stuff, etc)

You can't build an ecosystem around a product if you kill it after a few months. Arudino is only Arduino because they actually stuck around.

Intel owns Altera.

Providing a good FPGA CPU to run all the custom stuff is a great way to sell more chips.

This isn't aimed at makers so much as aimed at huge corporations with loads of money to burn on FPGA hardware, circuit design, and custom software.

It is the margins, the maker market is not the way server market works, and their management lacks patience.

Well, lately anyway. The 386EX [1] was supported from 1994 to 2006 with many interesting and "cheap" third party SBCs, replaced in 2007 by the Tolpai SOC line which was killed the following year. It's been all churn since then it seems.

You can still buy tons of 386EX chips and boards on eBay and even a couple first-hand (JK Flashlight) and there's a few modern homebrew designs out there.

1. https://en.wikipedia.org/wiki/Intel_80386EX

> which sounds to me like no out-of-order fancy stuff of the sort we've been used to.

Probably completely overkill for a soft-core.

On top of that, designing and verifying a core that people actually want to use is obviously much more difficult to do than going through HLS.

> They said "5 stage", which sounds to me like no out-of-order fancy stuff of the sort we've been used to.

That's inefficient for an FPGA softcore; wires are too expensive, CAMs are straight up awful, and memory latencies aren't too far off relative to the core clock frequencies to justify OOO stuff in the normal case.

> Well, I wrote a little 5 stage CPU FPGA program once (In Haskell compiled to Verilog :), but that's another story). It wasn't very hard.

Writing a 5 stage is easy.

Writing a 5 stage with no bugs is much harder.

Writing a 5 stage that talks industry standard busses and provides Debug/JTAG Support at high frequency and small gate counts is, well, an actual job.

Not saying you can't do better, but it's not a trivial effort.

I think that level of sophistication is typical of soft cores. If you need a high performance CPU you don’t use a soft core. You use a soft core when part of your FPGA project can be more easily expressed as a CPU, but still needs tight coupling with the rest of the FPGA.

This is meant to compete with Cortex-M1 and MicroBlaze, not with Cortex-A78 or Core i9 or something.

You don't have that fancy stuff in really low cost, embedded systems, or as part of the control path in a large, complex FPGA or ASIC design. Look at ARM Cortex M0+, M3, M4 or numerous RISC-V cores for microcontroller applications.

You get the core you need that meets the processing budget with as little cost, area/resources needed and with as little power consumption. That was true then and it is just as true today.

So it is not a processor it's a soft core. If you want a processor with this, you need to program an FPGA from intel.

I mean, it's a soft core like Nios I through IV. I know Altera would sell you a license if you wanted to dump it into a hard flow for some reason. I assume Intel will too? The Altera division seems fairly independent post acquisition.

Also Intel's not intimidated by the gate count niche of classic five stage RISCs; they gave that market up decades ago.

Yes, Intel will still sell you a license for NIOS if you want to harden it into your product.

Never heard about Nios III or IV, I feel only Nios II was in use, Nios V here means RISC-V core actually?

Xilinx has Microblaze which is similar to Nios II, both can boot 32-bit linux.

Oh, you're totally right. It was almost ten years ago that I used a Nios II, so I read the state space wrong without bothering to look it up. Lol, classic mistake on the internet.

A processor design in a HDL like Verilog or VHDL is not really a "program". It is a textual representation of physical hardware configuration. Seeing it as a program is usually the the root of problems faced by amateur HDL designers.

So true. The code describes real hardware - wires, gates, registers, memory macros. And those are finite resources. The FPGA tools allocate resources and map them to specific instances on the FPGA chip. In an ASIC there are more freedom, but the chip area, number of metal layers to route signals and delay, power sets constraints. Understanding that writing something in SystemVerilog, VHDL actually allocates physical, electrical objects is very important.

It is not bit patterns stored in a memory and interpreted, executed by something as a sequence of instructions. Routing congestion for example doesn't exist as a concept in SW.

It's a soft-CPU. It's not that it was designed 30 years ago, those just aren't meant to be deep and wide OoO cores.

It is not a program. It is a hardware design tuned to be efficiently mapped onto the primitives/resources in the specific FPGA fabric of the target devices. I'm fairly sure the actual source code is far from little. But the number of resources needed is quite low.

Given a clock and access to memory it will execute programs.

Could you elaborate on the "1990 style"? What do you mean?

Is it that it is a moderately pipelined, single issue, RISC like (explicit load/store, fixed width instructions, fairly large register file) CPU design? Why then, all RISC-V, ARM etc cores targeted for low cost embedded, IoT systems are 1990 style.

This is out of my realm, isn't it at least a little relevant to vet a (logical) design with an fpga before doing the full process? Or are those worlds things worlds apart?

The FPGA was the final target for this design. It isn't intended to go anywhere else -- its predecessor, Nios II, was also FPGA-only.

Little soft core CPUs like this are often incorporated into larger FPGA designs to handle sub-tasks that would otherwise be annoying to implement with pure logic. Think something like a simple CLI console to configure low level board functionality, etc.

You could make a physical chip out of this, but there are lot of O(1) costs that mean I am not just going to download Quartus, call up my local fab, and get me a toy CPU from this for fun.

In general yes. ASIC designs are prototyped using FPGAs. You often can't run at full clock speed. But can do orders more test cycles than in a simulator.

But FPGAs are also used as final target technology. When volume is too low, time to market too tight, where flexibility is important, FPGAs are used. Building an ASIC takes 12-15-24 months (depending on design complexity, target process), and a respin (due to an error) of parts of the design adds months before the product can be released.

Base stations for 3G/LTE/5G is a good example. They used to be built with a combination of ASICs and DSPs. But this took too long to develop, and was to rigid to handle upgrades (soft upgrade from 3G to LTE was/is a great selling point). Using FPGAs reduced development time, and provided generational upgrade in a much better way. Don't replace boards, just SW and FPGA bitstreams.

If you want to see some FPGA emulator monsters, look at Cadence Palladium, or Mentor/Siemens Veloche.

https://www.cadence.com/en_US/home/tools/system-design-and-v...

https://eda.sw.siemens.com/en-US/ic/precision/

They contain hundreds up to many thousands of FPGAs. Using support dev tools, you can take a large ASIC design and partition it over these FPGAs.

We once used four interconnected machines like these to emulate a large superscalar, OOO CPU design. It took a few days, but could go from release of reset to loaded OS. Something impossible with a SW simulation. Fun times.

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