The i3 through i9 are generally the exact same silicon. But yields are always variable. If you took the raw yield the actual i9 per wafer might only be 10%-20% which would not be economically viable.
So designed into EVERY Intel product (and generally every other semiconductor company's products) are "fuses" and circuitry that can re-map and re-program out failed elements of the product die.
So a failed i9 can AND DOES become i7, i5, or i3. There is no native i3 processor. The i3 is merely an i9 that has 6 failed cores or 6 "canceled" cores (for inventory/market supply management). Same goes for i5 and i7. They are "semi-failed" i9s!
This is how the industry works. Memories work in similar ways for Flash or DRAM: there is a top-end product which is designed with either spare rows or columns as well as half-array and 3/4-array map-out fuses. Further there is speed binning with a premium on EMPIRICALLY faster parts (you can NOT predict or control all to be fast - it's a Bell curve distribution like most EVERYTHING ELSE in the universe)
With this, nominal total yields can be in the 90% range. Without it, pretty much NO processor or memory chip would be economically viable. The segmentation is as much created to support this reality OF PHYSICS and ENGINEERING as it is to maximize profits.
So generally, to use your example, a non-ECC processor is a regular processor "who's" ECC logic has failed and is inoperable. Similar for different cache size versions - part of the cache memory array has failed on smaller cache parts.
So rather than trash the entire die which earns $0 (and actually costs money to trash), it has some fuses blown, gets packaged and becomes a non-ECC processor which for the right customer is 100% OK so that it earns something less than the ECC version but at an acceptable discount.
When I worked at Intel, we had Commercial, Industrial and Military environmental plus extra ones for "emergencies: e.g. parts that completed 80% of military qual and then failed - hence the "Express" class part.
We also had 10 ns speed bins which create 5-7 bins, and then the failed half- and quarter-array parts meant 3 more. So 4x7x3 = 84 possible product just for the memory parts I worked on.
For processors you could easily have separate categories for core failures, for ECC failures, for FPU/CPU failures. That takes you up to 100-200 easy. If you are simultaneous selling 2-3 technology generations (tik-tock or tik-tik-tock), that gets you to 500-1000 easy.
This is about "portfolio effect" to maximize profits while still living with the harsh realities that the laws of physics impose upon semiconductor manufacturing. You don't rely on a single version and you don't toss out imperfect parts.
BTW how do you think IPA and sour beers came about?? Because of market research? Or because someone had a whole lot of Epic Fail beer brew that they needed to get rid of??
It was the latter originally, plus inspired marketing. And then people realized they could intentionally sell schlock made with looser process controls and make even more money!