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Comment by LeifCarrotson | Hacker News Reader

It's a particular module for the Xilinx Artix 7 XC7A100T, made by a Shanghai-based integrator. As an individual user, you could buy these on Aliexpress, from eBay resellers, or from Amazon resellers. Facebook presumably has an arrangement with the contract manufacturer that's not going to be possible for an individual developer ordering ones and twos to replicate.

However, to modify the HDL, you'd need a $3,000 license for Xilinx Vivado, which is pretty much a nonstarter for amateurs.

[1]: https://store.digilentinc.com/arty-a7-artix-7-fpga-developme...

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Thank you for id'ing the module. I can now see how using this would work for Facebook's needs.

I think the XC7A100T is supported by the free (and limited) edition of Vivado [1]. Of course, the confusion about what you can and can't do with the HDL is in itself a barrier to open source and hobby work. This is true even when the work is theoretically possible and everyone has the best of intentions. <sigh>

[1] https://www.xilinx.com/products/design-tools/vivado/vivado-m...

That is not true. First of all, the reason why we used the Alinx module (which you can buy of ebay as well as Amazon), was to make it easier for the community to manufacture and build. Our internal version of the time card does not include the module! The second piece about the XC7A100T, you do not need any license to do any development as the free version of vivado is more than enough to work with. Give us a bit of time and we will have a fully functional open HDL ready for you to add things. It is very easy to sit down and nag about a project. I want you to understand that I had only one goal in mind when I released this project to public and that was allowing others to have a head start to work on time related project. Of course, I work for Facebook and I try to help my company with new technologies as a researcher, but helping the community and releasing the source code (to whatever I had) is just a core value of how I love to support the community.

you don't need vivado to modify the hdl, you need vivado (or some other proprietary xilinx toolchain) to produce the bitstream which actually deploys to the fpga.

That's a level of nitpicking that I didn't bother with.

Of course the Verilog or VHDL is just plaintext, which you can modify anywhere, but to actually do anything with it you need to compile it into a bitstream.

It does make me wonder if someone could set up a CI server to get around proprietary compilers like Vivado. Point the community resource at your source and get back a binary! Obviously you'd need to strip the license ID...

i didn't mean to nitpick and it's not nitpicky since there are now open toolchains (though not for xilinx) that you support verilog as a frontend

http://www.clifford.at/yosys/ http://www.clifford.at/icestorm/

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