I'm afraid I don't have any articles to direct you to. I can give you a little detail of how they do it with RAM. DRAM is just a huge array of cells. The array itself is made up of repeated sections of a block. These blocks are independently wired and have on-die logic for testing (simple memory check). The blocks which pass testing are configured by blowing fuses so they're connected to the normal input/output logic, and the broken ones have fuses blown to disconnect them from the power rails.

They slightly overbudget the number of blocks when designing. This way if a few blocks are faulty they still have a working RAM chip. If a whole bunch of blocks aren't working, they can still sell it as a half- or quarter-capacity chip. A 8, 16 and 32 gigabit RAM chip in the same process from the same manufacturer may well have the same die inside, with different fuses blown.

This isn't new; it's been done since at least the 1980s. It's my understanding the same thing is done with cache and cores and even execution units on modern processors, but I would assume with a great deal more complexity.

The book “VLSI test principles and architectures: deign for testability” edited by Laung-Terng Wang et al, is quite good.