Warp-V: A RISC-V CPU Core Generator Supporting MIPS ISA

Interesting. Anyone knows what's the benefit of TL-Verilog compared to a next gen HDL like nmigen?

Robert Baruch used it extensively for his own RISC-V CPU implementation. Its channel is well worth watching for those interested in CPU design.

https://www.youtube.com/c/RobertBaruch/videos