Comment by jonnycomputer | Hacker News Reader

Comment by jonnycomputer | Hacker News Reader

>The Ena.Computer is designed using 550 double triode 6N3P electron-tubes, all configured as identical 5 input NOR gates. Registers and counters are built from these single NOR gates and combined into master/slave D type flip flops, an 8 bit ALU, and all latches and buffers.

In my computer science program, we had an old school prof who insisted we build a virtual CPU using only fundamental components. No VHDL for us! We wanted a JK flip flop? Here are the logic gates. Wire them up baby. The only thing that came for free were the logic gates, a clock, and probes. Some students complained about it; and I get it, it was a very old-school way of doing things. But I can say that I intimately understood my 5-staged pipeline CPU, because I designed it from the ground up, and spent hours wiring every component. I also had plenty of time cursing myself for some stupid design decisions I made along the way. The only thing that might have made it better if we were tasked with actually building it out in actual hardware. I'm a fan of those homebrew cpu's out there. Maybe not practical from computing perspective any more, but sooo cool.

http://homebrewcpu.com/

https://hackaday.io/project/178826-pineapple-one

The VLSI equivalent version of this is to build a cpu by manually placing the N/P diffusion regions, the gate poly, the metal contacts, and the metal wires in your EDA program. The conclusion is to either export it as a spice model and simulate it electrically, or actually get it fabbed on an old process node.

Week 1-2: construct your own standard library of logic cells (I.e. design the layout of the not gates, nand gates, etc).

Week 3-4: compose these std cells into latches and flip flops.

Week 5-6: verilog implementation of your cpu. Used primarily as a model.

Week 7-10: lay out your CPU. Everything from the register file to the ALU. Placed and routed by hand.

Week 11: SAPR the instruction decoder/control logic and then integrate it into your custom layout. Ok so you can’t brag about your layout being 100% custom anymore, but you learned more by doing it this way :P

Week 12: write an assembler; compile a simple assembly program.

Week 13-14: run it on the CPU; explore the limits of your CPU (clock speed, etc).

Well the timeline will vary, but that’s the idea. I think the only feasible way to do that is as a team project spanning multiple quarters. Honestly one of the most rewarding projects I’ve ever done & would recommend to any prof out there who wants to push their students.

I spent many hours in http://www.cburch.com/logisim/ during my program doing the same thing. It was a great feeling to finally get a sub component correct and then copy it around in the next layer up.

yeah, that looks similar to the software I used. yes, and great feeling too, because I was in control of my design (only spec was it had to have at least 5 stages in pipeline). I remember the first time I got a program running. Felt really good.

>who insisted we build a virtual CPU using only fundamental components. No VHDL for us!

A little convoluted, but apparently a couple of people have coaxed Verilog and/or VHDL into understanding 74xx logic chips: http://pepijndevos.nl/2019/07/18/vhdl-to-pcb.html

We did the same in my EE program, though we were allowed to use a ROM for the microcode and some 8-bit registers from the TTL family. I never had time to build it either as it’s too much for a single semester class.

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