Geohot/twitchcore: A RISC-V core, first in Python, then in Verilog, then on FPGA

Livestream (8h20m): https://www.youtube.com/watch?v=camQ9QeBY9Q

I think he more or less gave up when he realized he needed a bus width of 38000 bits.

Geogot gives me Fabrice Bellard vibes.