Comment by johndoe0815 | Hacker News Reader

Comment by johndoe0815 | Hacker News Reader

The CM1 was a massively parallel computer built by Danny Hillis in the context of his PhD thesis at MIT and commercialized at Thinking Machines, Inc. in the mid-late 1980s. The machine had up to 65536 very primitive CPU cores (more or less just a simple ALUs) interconnected using a 27-dimensional hypercube - and a fascinating array of LEDs, indicating the activity of each of the CPUs (and just a fake display showing random patterns on later machines such as the CM5). You had to use a high-end workstation such as a Sun 3 or Symbolics Lisp machine to operate the CM1. In principle, the CM1 was a (very expensive) single user machine, but larger configurations could be configured into up to four independent partitions, one per user.

One famous person working on the CM architecture was Richard Feynman; the story of his optimization approach to reduce the number of buffers in the router chip of the CM1 is worth reading: https://longnow.org/essays/richard-feynman-connection-machin... (this article also links to a TEDx talk by Danny Hillis).

If you are interested in more CM1 hardware details, Danny Hillis' PhD thesis can be downloaded from http://dspace.mit.edu/handle/1721.1/14719

CM-1/2 is not exactly computer, it is more of a massively parallel SIMD computation accelerator. While AFAIK the CM-1 microsequencer has some limited ability to handle control flow it is there mostly in order to futher compress the instruction stream coming from the front-end workstation (which came over two wonderfully thick 50-pair ECL cables) and most of the actual programmed controlflow is done in software on the front-end side. It's architecture is somewhat reminiscent of FPGA. But while you can freely program the individual macrocells in FPGA, all of the CM "CPUs" have the same configuration, but this configuration can change each clock cycle (see Fig 4.1 in the dissertation and take note that the ALU is essentially an freely configurable 8x2 LUT).

CM-1/2 is not exactly computer, it is more of a massively parallel SIMD computation accelerator.

Right. SIMD was something people tried doing before they could get enough transistors to give every node an instruction decoder. It's useful for a narrow class of problems where special purpose hardware or an FPGA isn't justified, but the problem is so regular that SIMD will work. This niche is not large enough to keep a company in business.

(There were a long series of strange architectures tried in that period. Transputers. Hypercubes. Dataflow machines. The Cell. All too hard to program and not general purpose enough.)

I would have liked to see a debate between Chock Moore and his Greenarrays chip and a Danny Hillis and the connection machine.

Despite surface similarities, the two projects are very differnt (speed vs energy efficiency, simd vs mimd, lisp(*) vs forth)

But to program them you must keep the same mindset, I think, and both are best seen as macro-FPGAs.

Surely "27-dimensional" must be wrong? 65536 is 2^16; what would an extra 11 dimensions be for?

(The OP says 12-dimensional; the Wikipedia page says 12-dimensional in one place and 20-dimensional in another; the latter seems like it must also be wrong. I wonder whether it's 16+4 where the correct figure is 16-4, the idea being that there are 2^4=16 processors per node or something like that.)

It sure looks like 12 is the right number and is indeed 16 minus 4.

http://public.callutheran.edu/~reinhart/CSC521MSCS/Week7/Con...

"For a fully configured CM-1, the network is a 12-cube connecting 4,096 processor chips (that is, each l6-processor chip lies at the vertex of a 12-cube)."

Oops, no idea where I got the 27 from, thanks for the correction. Grading too many exams is confusing...

We had a Thinking Machine at the University of Minnesota. The person who was in charge of it learned to determine if the code running on it was efficient by watching the patterns of the LEDs.

Was it, essentially, a video card -- before video cards existed -- in a big box?

The architecture is significantly different from what you would find in typical GPU. But the programming model can be considered similar to early days of GPGPU programming on hardware that was not designed for that usage (ie. no control flow instructions, just giant SIMD number crunching thing running somewhat decoupled from host computer).

No, early Crays were a lot more like that though.

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