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Comment by bcantrill | Hacker News Reader

Barefoot didn't die -- they were acquired by Intel, who has continued to invest in it with the development and introduction of Tofino 2.[0] Moreover, P4 is not/was not Barefoot alone; to take an example that's relevant to us, the P4 application working group working on the In-band Network Telemetry Dataplane Specification[1] includes participation from Alibaba, Arista, CableLabs, Cisco Systems, Dell, Intel, Marvell, Netronome, and VMware.

Disclosure: We are using both Intel Tofino 2 and P4 at Oxide and we (obviously?) think it's pretty interesting.

[0] https://www.servethehome.com/intel-tofino2-next-gen-programm...

[1] https://github.com/p4lang/p4-applications/blob/master/docs/I...

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I would expect to see Intel pushing P4 heavily over the next year. P4 will almost certainly be involved in the roadmap for their recently released IPU (a SmartNIC needs some type of programmable substrate). Also, their data platforms group had been recruiting heavily around the Barefoot Networks / P4 angle. AND, just this morning, Pat Gelsinger announced the data platforms group is being split into two groups —- one of which (the Network and Edge group) to be headed by Nick McKeown, former chairman and cofounder of Barefoot Networks, as senior vice president [0].

[0] https://www.lightreading.com/5g/intels-reorg-puts-nick-mckeo...

Are these the jobs based in Israel?

Primarily based out of Santa Clara, California. All of the Santa Clara roles on this page [0] are in the Barefoot Switching Division (BXD) of the Data Platforms Group. It makes sense given the Barefoot Networks headquarters were in Santa Clara.

[0] https://jobs.intel.com/page/show/US-Connectivity-Jobs

Quick quote[1] on what a SmartNIC is:

> The Silicom FPGA SmartNIC N5010 features an Intel Stratix 10 DX FPGA with integrated high bandwidth memory (HBM) and Intel Ethernet 800 series adapter.

4x100G. Double slot.

There's also a C5000X platform, with I believe only one board out right now, which is again an FPGA based add-on card, 2x25G, and also has an on-card Xeon-D processor.

Just a little reminder here at the end, AMD is still trying to get it's acquisition of the biggest FPGA company on the planet Xilinx to go through. And my general assessment of P4: P4 definitely is a strong contender for a tech which can get these fancy awesome transciever-heavy FPGAs to see more adoption.

[1] https://www.hpcwire.com/off-the-wire/intel-announced-two-new...

You can probably remove Netronome from the list. They stopped developing/supporting P4 and mostly dead. They tried to switch to ebpf but I don't think they succeeded. Sad story

It does kinda look like Tofino 2 was delayed two years by the acquisition, eerily reminiscent of the FM6000 delay that cost Fulcrum all of its market share. Tofino 3 should probably be sampling by now.

What does tooling / debugging for p4 look like? How do you inspect what happens inside a p4 dataplane?

Context: I work on a L4 load balancer written in ebpf / XDP. Debugging that is still too hard even thought it's all software and open source.

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