SiFive P550 Core: High-Performance RISC-V Processor | Hacker News Reader

SiFive P550 Core: High-Performance RISC-V Processor

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191 pointsandrewnc84 comments

Hopefully the recent acquisition rumors don't spell the end of this healthy competition between x86 and RISC-V.

I wonder what we'll see as a result of this partnership with Intel:

SiFive also confirmed that the IFC RISC-V application development platform will use the Performance P550 core on Intel's 7nm Horse Creek platform.

Link: https://www.phoronix.com/scan.php?page=news_item&px=SiFive-P...

SiFive are definitely amongst the most interesting players in RISC-V right now.

Though there other organisations doing things, e.g. the PULP Platform: https://news.ycombinator.com/item?id=23768080

I hope that the acquisition doesn't go through, more competition would be great, and perhaps within a decade a wider commercial RISC-V ecosystem could emerge.

There is no "healthy competition between x86 and RISC-V".

Only between RISC-V and ARM?

ARM is a collection of many different cores. So yes, RISC-V probably competes well vs ARM-M, but I wouldn't say that RISC-V competes against ARM-A (which is starting to become big enough to compete against x86).

Just because ARM-M and ARM-A shares an instruction set doesn't mean that those chips are anything alike. Heck, ARM-M0+ is a completely different chip than ARM-M4.

ARM-R is roughly the target of RISC-V. (Realtime cores).

The core in this article wouldn't be a very good ARM-R core being OoO. It's about the same niche as an A72 AFAICT. So RISCV is already nipping at the heels of the ARM application core space.

ARM Cortex R8 is out of order.

https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-...

And AFAIK they didn't really get any takers there either because it didn't really make sense. I think ARM was hoping for a market of large legacy codebases (think cell modems) where the heavy hard realtime work had been migrated to fixed function IP blocks, DSPs, etc. years ago, but the vendor didn't want to spend the time migrating their RTOS to ARM-A from ARM-R for the intermittent, non realtime, but still compute intensive work. You can sort of see how they didn't get any uptake with how the marketing changed pretty heavily with the R82 towards storage vendors instead of 5G. And RISCV doesn't have even the hope of that network effect to bank on.

I'd also expect features like per core TCM if this core was targeting ARM-R niches to at least break away from the non determinism of the memory hierarchy (particularly a multi core memory hierarchy!), but I don't see that here.

There are multiple vendors now selling RISC-V products that compete with ARM-A as well.

Its not as far alone as the lower end but it defiantly happening as well.

The SiFive P550 is described as competing against the ARM Cortex A75 application processor, which was announced four years and one month ago.

Previous SiFive cores compete against the A72 (announced but not yet shipping that I know of) and A55/A53 (shipping in the BeagleV "StarLight" beta and HiFive Unmatched and probably unannounced embedded applications).

In the four years since the A75 ARM has announced the A76, A77, A78, and A710 as annual incremental improvements (the most recent of which are not available in products yet), plus in a new higher-end line the Cortex-X1 and X2.

So ARM is not standing still, but SiFive is catching them at approximately two years of ARM progress every year i.e. closing the gap by one year per year.

Yeah, I really can't imagine how one would class it as healthy let alone even a serious competition. x86 and ARM, however, are starting to have a real battle with ARM owning mobile, making headwinds into laptops and desktops at Apple and multiple vendors producing meaningful server chips.

ARM is making headwinds into server as well now.

It's hard to tell apples->apples when you can't buy the leading edge ARM servers outright AFAIK. There's a good argument that it's in the hyperscalers' best interest to discount ARM usage to even below their breakeven to put negotiating pressure on their x86 core suppliers as long as they balance the costs well enough.

Merchant ARM server is mostly dead unfortunately. Hyperscalers like AWS are making their own SoCs in house however. Amazona acquired Annapurna labs for that purpose.

Personally I see there being more market overlap between ARM and the P550 core however. Samsung, Qualcomm, Renesas are all planning to bring RISC-V cores to market. With performance between A75 and A76, I could see the P550 being a pretty major disruptor. We already know some RISC-V chips are gaining traction in embedded, IoT, RF, micro-controllers, etc. Automotive looks like the next big market for RISC-V to me.

Ah, this isn’t true.

Ampere is very competitive and Oracle have made huge investments into that platform, with Cloudflare etc looking at it very seriously as well.

Arm on servers is just getting started.

With RISC-V and SiFive, companies are able to build their own optimizations and make them MORE proprietary. I'll cringe if VLC will come with various versions: x86, M1, IntelRISC-V, QualcommARM, SamsungARM, SamsungRISC-V etc.

There was no "healthy competition between msn and google". There was no "healthy competition between Blockbuster and Netflix". There was no "healthy competition between Barnes & Noble and Amazon".

Lack of competition today does not belie there never being competition. I would argue that anti-trust should be taken against killing/buying your competition when it's still in the womb, see Instagram-v-Facebook, WhatsApp-v-Facebook, InstagramStories-v-snapchat

It's ridiculous to compare RISC-V against x86 as serious competitors in the same market. Shipping RISC-V chips are currently about 25 years behind x86 in microarchitecture (similar to Pentium) and 20 years behind in performance due to using more modern process nodes and higher MHz.

Similarly, shipping RISC-V chips are currently six years behind ARM's A53.

The P550 closes the gap to ARM to 4 years, and to Intel probably about 12-15 years with P550 and A15 both most similar to Core 2 in the Intel line-up.

That's a highly-usable level of performance, especially when paired with more modern RAM, SSD, and GPUs than were available in Core 2 systems.

I'm genuinely puzzled as to whether this absolutely factual comment was downvoted by RISC-V haters or RISC-V fanboys lol.

I hope they release an update of the "Unmatched" motherboard with one of these chips. I'm reluctant to spend ~$700 on a platform which uses in-order cores which are presumably designed for low-power devices.

(Yes, I appreciate I may not be the intended audience for that board, but I would still like to build a RISC-V based desktop one of these years)

The P550 core in the title is actually a 3 way issue OOO core with near A76 performance, but fair point on the dev boards. Hopefully Intel's dev board or some alternative will provide a lower cost option.

You wouldn't be happy with the Unmatched. At 1.2 GHz, it's slower than a Rpi4. Even a Beagleboard-X15 (2 core armv7) is faster.

Well, naturally. The Pi 4's A72 cores are much more sophisticated than the cores in the Unmatched. Comparing it against A53 or A55 boards (Pi 3, Odroid C2 or C4) is more appropriate.

You don't buy a HiFive Unmatched because it's faster or cheaper than an ARM-based board. It's obviously not.

You buy a HiFive Unmatched because you specifically want to run or create RISC-V software because you believe that will be important in the future and the Unmatched is currently the highest performance way to do that, certainly for single-threaded code or for running a full desktop OS with accelerated GUI.

You get get more overall multi-threaded RISC-V performance running QEMU on an x86 machine with 8+ cores. That's probably going to cost more. But you might already have one that's not heavily used.

It's for sure an interesting result but honestly, perf/freq is yesterday's spec. What matters in 2021 is perf/W and perf/$ and there is no information on either of those metrics.

They mention “performance/area” as being dramatically better than Cortex-A75. I’m not familiar with whether area is expected to relate to power usage.

perf/area comes with a huge number of caveats and it basically doesn't mean anything as given.

For example, the exact same verilog, on the same process node at the same foundry, can synthesize to very different areas depending on the standard library used. They come in a lot of varieties with a lot of different trade offs.

For even more detail, the SkyWater130 node, which has been popular on HN lately and is public so we can actually post links to it, has 6 different mappings that are possible. Note, some are called high speed, or high density, etc. You get the idea.

https://skywater-pdk.readthedocs.io/en/latest/contents/libra...

I'm not even why we're supposed to care about a newly launched core beating one that was released in 2017. If that's the bar they've set, I'm not exactly wowed.

Gotta start somewhere

Because the ARM core still has a large market and not every application need the maximum performance so having competition in that market is not good.

And you are not 'supposed to' care. You can care if you want, and ignore it if you want. So I don't really get your attitude here.

ARM has a head start of many years and billions of dollars. The fact that this is comparable to an ARM processor of a few years ago is a good sign.

So we're grading on a curve.

Look at the trajectory for ARM catching up with Intel. The trajectory for RISC-V is even faster. That’s at least mildly indicative of where the future is headed.

Past performance is no indication of future returns, especially when it's someone else's performance.

The first 4 minute mile record was set in 1954. Now there are a bunch of people who have done it. Once formerly new techniques start to be known and distributed, it becomes much easier to catch up.

Remember, RISC-V doesn't have to beat ARM -- only come close enough that the price differential outweighs the performance difference. This is already happening on the low-end end and it's only a matter of time (IMHO) before this becomes reality on the high-end too.

Not every task requires the latest and fastest CPU. ARM makes and sells a huge number of smaller slower lower power cores -- numerically far more than the high end cores in SmartPhones -- and RISC-V is there competing with all but the very high end.

SiFive likes to include just enough resources to do well on their benchmark du jour (was dhrystone, now SPECint) and leave out the rest. So they end up comparing an Arm core with NEON against their RISC-V cores with no SIMD/vector support for example.

Previous cores had no vector support because the V extension that provides for it was nowhere close to being standardized. In fact it's yet to be ratified at present, so one may want to wait for that before choosing a V-capable core for real, actual use.

Which is fine because what would normally be handled by the SIMD will be custom silicon for most customers and have a 4-100x speedup over what SIMD could provide.

>They mention “performance/area” as being dramatically better than Cortex-A75.

The P550 pref / area based on Intel 7nm equivalent to TSMC 4nm / 3nm that is better than the ARM Cortex A75 released in 2017 on TSMC 10nm.

Number using Intel CPU's 7nm, normally Custom Foundry of IFS tends to offer lower density but higher flexibility. So this is more like a best case scenario.

I am also suspicious of the Intel 7nm number. There are some possibility this is actually an Intel 10nm renamed to 7nm for custom foundry partners. ( Intel 10nm being equivalent to TSMC 7nm )

No, the area numbers quoted are for TSMC N7. You can look up comparable A75 die area numbers for N7 as well. A Cortex A76 on TSMC N7 takes up 1.27mm with L2 included. A P550 takes up 0.38mm.

As per Intel announcement and Anandtech [1] while not explicityly stated, the P550 number are from Intel 7nm Intel Foundry Services. I am not sure where that TSMC N7 came from.

[1] https://www.anandtech.com/show/16777/intel-licenses-sifives-...

What about perf/degree of safety?

Can I interest you in a nice Hercules Cortex-R?

You can until I look at the errata pages. Emphasis multiple pages.

If Ambiq's chips are real, they're orders of magnitude ahead of everyone else when it comes to perf/W.

The following is speculation on my part, so I'm inviting discussion. To some extent it feels SiFive is trying to turn RISC-V into ARM by locking it up in patents while at the same time holding the keys to the ratification of the various extensions, some of which (H-extensions being good example[1]) have been stuck without much development, slowing down sw support and making it difficult to upstream[2] what has been developed so far. Meanwhile, WorldGuard is available and perhaps thriving as closed, commercial IP. It feels like there could be some conflicts of interest there and, honestly, if Intel bought SiFive, it would at least make those intentions blatantly obvious.

[1] https://lwn.net/ml/linux-kernel/CAAhSdy0F7gisk=FZXN7jmqFLVB3... [2] https://lists.riscv.org/g/tech-privileged/topic/risc_v_h_ext...

IIRC, H extension was set aside because much of the desiderata for H could be achieved more simply by reusing the S (supervisor mode) extension.

Do you happen to have a link to this discussion? I couldn't find anything associated with the spec commits on [1].

One of the aspects folks were looking forward to seeing is the specification of the 2-stage IOMMU, which S-mode or other parts of the spec don't address per the lengthy discussion on [2]. Thanks.

[1] https://github.com/riscv/riscv-isa-manual/commits/master/src... [2] https://arxiv.org/pdf/2103.14951.pdf

The H-Mode has been removed, but people usually still call it the H extension.

Good point H-mode != H-extension. H-extension is very much still alive, afaik, and that is what I referred to.

> RISC-V into ARM by locking it up in patents while at the same time holding the keys to the ratification of the various extensions

Would you please provide a direct link to some of those patents or discussion?

The thread at [1] if I read it carefully does not mention patents, but seems to be a prelude to submitting the RISCV kvm stuff to staging that Greg KH complained about a while ago.

The press release mentions that this is a triple-issue OOO design. Probably based on BOOM v3/SonicBOOM architecture[0], given what we know of previous SiFive designs.

[0] https://github.com/riscv-boom/riscv-boom

From the press release:

"Evolved from the previously announced SiFive U84 microarchitecture,"

The U84 was a from scratch, in-house design.

Go work with System76 and get me a RISC-V RV64GCV Laptop. That would be awesome.

And a tablet computer.

AllWinner will likely deliver one of those in the near future.

If they do I hope those chips get better mainline Linux kernel support than the ARM based ones. The work the Armbian devs are doing is amazing, but they are still missing drivers from the manufacturer. Mainly for proper graphics and video encoding/decoding. The only operating system where this works well is in Android with an archaic kernel.

The CPU support is already pretty good and for example Huawei is pushing important Linux kernel patches.

What you are talking about is drivers for peripherals, which is are SoC-level issues, and really up to the partners (like Allwinner, SiPeed, etc). So far documentation is the most critical part and it's a very mixed bag. I think this will be much like the Arm experience, albeit everyone is at least using device trees these days.

I have a C906 and while it's fun, it's very very slow by 2021 standards: single core, scalar in-order @ 1.0 GHz with no L2$.

The upcoming BeagleV is a lot faster (I have the beta): quad core, dual issue in-order @1.5 GHz (TBD) with 2 MiB L2.

I'm expecting (guessing) that the triple-issue OoO P550 would be 5-10X faster at iso-frequency, but if history repeats it'll be four+ years before we see it in silicon for sale.

Maybe 2 to 2.5 years. The U74 core in the BeagleV and Unmatched was announced October 2018. If not for COVID it probably would have shipped six months ago.

The C906 core in Allwinner D1 SoC will make an excellent competitor to the Pi Zero when it ships on the promised $10 to $15 Sipeed and Pine64 boards later in the year -- and that will be a real price where you can buy as many as you want, not the "$5 but you can only buy one" fake Pi Zero price.

The $99 "Nezha" board with the D1 is of course not value-competitive for that performance level. It's a manufacturer's (i.e. Allwinner) prototype board for volume manufacturers such as Pine64 to use to develop software while they work on their own board.

The same goes for the HiFive Unmatched. It's not intended for volume production, it's for developers to use to prepare software for later high volume boards (including the BeagleV).

Intel have announced they'll be making them next year: https://www.anandtech.com/show/16780/intel-to-create-riscv-d...

Is it coming with some SATA interface?

and a little desktop box. Gotta be quicker than a Raspberry PI 4 though.

Anything RYF certified. Nevermind the manufacturer.

I hope you enjoy secret proprietary blobs in RYF hardware.

RYF certification decreases freedom, it doesn't increase it. The qualification for RYF is that the user not be able to see any blobs, not that they don't exist. As a result, manufacturers hide and bury the blobs in order to achieve compliance. Meanwhile, more open devices with optional replaceable blobs are denied certification.

Thread on just how out of touch the FSF is with all this, and how they do not support real, objective user freedom: https://twitter.com/marcan42/status/1377899929209774081?s=19

How does RISC-V places itself in market? What would be the advantage of going RISC over let say ARM (or x86)?

as backup incase Nvidia manage to buy ARM and squeeze all the fabless companies

And what if Intel buys SiFive and we are back to stunted RISC-V cores?

is RISC-V a closed platform like ARM? is RISC-V an open source platform or not? what does Intel buying SiFive gotta do with RISC-V?

RISC-V is not closed, but the best RISC-V cores are.

If Intel buys RISC-V, the entire ecosystem could be set back.

Maybe, but others will also offer high-performance cores since it's an open spec and there are no licencing barriers to doing so.

I do hope so. The Xuantie cores are not yet comparable AFAICT.

Intel buying SiFive would be one of the best things to ever happen to RISC-V.

They bought Alpha to strip it for parts (Sandy bridge looks an awful lot like ev8) and because nobody else could make alpha chips which killed a competitor to x86.

The game has changed.

If they buy SiFive, that encourages even more investment into the ISA. They can’t kill it by doing that and even if that were the real goal, M1 competition would just convince everyone they were lying and working in secret.

What Intel brings to the table is talent and money. They have a ton of amazing developers worth decades of experience. They would think nothing of throwing two or three teams at the problem even if most of that money would be wasted.

Then there’s software. Intel realizes more than anyone just how important good software is to an ecosystem. A couple billion dollars for a thousand man years of developer time is also not much to them in the grand scheme of things. They’ve wasted way more money chasing actually bad ideas (see all their GPU attempts through the years).

ARM is wary of RISC-V, but they’d be actually scared if they knew Intel was about to throw massive amounts money into R&D.

I think Intel would develop extensions and variants on top of RISC-V, and clever techniques for implementing RISC-V, that they would then patent heavily.

This would be terrible for everyone else currently having fun developing RISC-V cores, because they would find the next obvious RISC-V-specific improvements that they think of on their journey would tend to be patented, as Intel got there just before.

After a few of those, the fear would start to discourage people in the open source world from even trying to make big improvements to RISC-V designs - the same way people without funds steer clear of their own x86 and ARM processor designs just to keep safe, even though patents on 20+ year old designs should be all expired by now.

The core of RISC-V is already out there. It includes all the most critical parts and they aren't likely to be patented.

Intel wouldn't own the ISA and be (effectively) the only game in town. If they refused to license at reasonably costs, other companies wouldn't add the feature and it simply wouldn't get much use by developers. This has already happened to some extent with the current duopoly.

Patents also cut both ways. Intel hardly has a monopoly on good ideas. For any idea they want to patent, they have to be very sure that one of the myriad other companies, students, and hobbyists haven't already had the same idea too otherwise their patent will simply be invalidated.

Finally, if Intel has come up with a good ISA extension and is willing to license it to others for a reasonable cost, I think that's a great boon for everyone.

RISC-V is license and royalty-free. This provides more freedom to manufacturers to experiment and optimize for specific workloads something helped by RISC-V's modular design. Also its simpler design makes it attractive to hobbyists as well.

But in this case (SiFive) the core IP is proprietary.

So what makes this better than an ARM A78 or X1?

It's cheaper. That's pretty much it.

RISC-V isn't in a market. SiFive is, and I think their positioning is "high performance, but cheaper than ARM". "Going RISC over let say ARM" doesn't make sense; ARM is RISC. That's what the "R" in "ARM" stands for: "Acorn RISC Machine".

> said Amber Huffman, Intel Fellow and CTO of IP engineering group at Intel.

Hope intel doesn't infect it with IME.

Yeah, that's a very serious concern.

The existence of a RISC-V core with a management engine wouldn't preclude the existence of RISC-V cores without management engines.

Nothing with bitmanip yet? :(

BitManip is currently frozen and in the 45 day Public Comment period before ratification.

Expect chips in 9 to 12 months, minimum.

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