Wonder how Forth and Forth-chips can help here.

I imagine a tiny Forth, which interprets larger Forth, which implements C enough to compile old TinyCC/GCC and start the chain of rebuilds (as explained in stage0).

As for hardware, a schematic for Forth would be simpler than schematic for generic RAM machine. But if not, intermediate minimal RISC-style machine language is still fine.

Steps to reach that level of hardware are already describe in NandToTetris, so in the end anything capable of implementing NAND/Fanout/Wiring can be used to run bootstrap chain.

Then we only have to make sure HW and SW implementers don't introduce bugs.