From reading the documentation, it appears that their open source tools start with Verilog RTL files that have been simulated with Synopsys VCS, Mentor Graphics Questa, or Cadence Incisive Enterprise Simulator.
That said, one could probably use the free (but not open source) Vivado HL WebPACK to create and test the RTL design and then follow along with the Skywater tools. But that way, the way towards the FPGA would still be closed source and only the path from FPGA on to ASIC would be open.
Further down the rabbit hole, I read about https://github.com/icebreaker-fpga/icebreaker which appears to be a tiny Teensy-compatible open source FPGA board with accompanying open source tools. Yay!
Thank you very much for bringing all of this to my attention :)