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Removing L3 frees up transistors to be spent on L1/L2. On a modern processor the vast majority of transistors are spent on caches.

Why this might help, ultimately, because the latency for getting something from L1 or L2 is a lot lower than the latency from L3 or main memory.

That said, this could hurt multithreaded performance. L1/2 are used for 1 core in the system. L3 is shared by all the cores and a package. So if you have a bunch of threads working on the same set of data, having no L3 would mean doing more main memory fetches.

I think the idea is by removing L3 has allowed for an increase of both L1/2.

I think he meant "despite not having L3"

Apple will invent L3 for workstation-level CPU.

Wild theory: for workstation-class systems, the 8/16 GB of on-package memory becomes "L3", and main memory can be expanded with standard DIMMs.

If you could get a Mac Pro with 32 to 48 firestorm + 4 icestorm cores with tiered memory caching and expandable to 2TB+ DDR4/DDR5 DIMMs. That would be an impressive machine for the small amount of wattage it would draw from the wall.