The thing here is balancing core speed vs “effective” memory latency (factoring in cache hits, misses, etc).
Cache management is a hard problem, and the equilibrium point is load dependent (i.e. depends on what type of program you use).
AMD has been smart enough to understand that sometimes it’s better to just brute force your way in (with higher cache sizes) than being super clever about how you handle it.
They add massive caches as a side effect of having loads of cores enabled by their chipset designs.
I generally err on the side of “I’m not as smart as I think I am” in these kinds of discussions. It’s not that I can never do it. I’m sure if I studied it a bit I could. The reason is that 99% of the lines of code I’ve ever written don’t warrant that kind of attention. I’m sure there are uses like when you’re writing some core fundamental algorithm in the fields of compression, crypto algorithm, hash, video processing, etc etc etc. I don’t work in those spaces though so the benefit is much more marginal.
It’s possible 192mb is enough to start needing some explicit memory management. It makes the coding model much more complex though. And in a greedy software system where your code isn’t the only one running, such complexity doesn’t necessarily net overall wins. It’s the reason we have drivers and OSes even though we started with each piece of content bundling explicit HW support (at much better perf generally)
1. Heat doesn't go away with layers and gets harder to cool. 2. These are still layers. You want each layer to be as flat as possible. As the layers deform you lose the ability to cleanly add more layers.
Current lithography is very much based on the notion that everything is flat.
Now what we have over the years seen interest in is adding processing cores to the RAM itself and maybe having a small dedicated processor for some tasks attached to the RAM may well prove viable.
Imagine if we didn't have any CPU or RAM sockets/slots and just a row of slots you addedd a module that had CPU/RAM in one and can just add more upto the slot limit. But then, that is kinda how GPU's have gone already in many aspects and look at how much RAM they hold and how large the cooling solution for them is. That gives you an idea of the cooling needed for large amounts of processing and RAM when closely packaged.
I think we call these 'GPUs' today.
> just a row of slots you addedd a module that had CPU/RAM
As you mentioned, GPUs fit this description, but some PCIe devices are full-blown embedded systems.
I think we're at the point where the only major improvements will take place on the CPU die itself.
Whereas, what the parent poster is describing would be true MIMD: a bunch of tiny cores each with its own on-board RAM, its own instruction pointer, and then a bus (or a bunch of busses) fast enough to feed them all data from (probably NUMA) main memory.
GPUs don't provide any advantage for running e.g. a high-concurrency Erlang application server. But a true-MIMD system would.
DRAM is incompatible with the logic family used in CPU making, though attempts were numerous at trying to work around that. Every few years, there are somebody coming with claims of passable CMOS+DRAM tech, but none got adoption so far.
A very curious case, and a very clever hackery with a custom SOI process. It's still very, very far from coming to mainstream chips.
"Both it and all levels of cache in the main processor from level 1 use eDRAM, instead of the traditionally used SRAM."
So if you just first make CMOS, and leave empty space nearby protected by something to do DRAM later, it will be very hard to fit into the tiny remaining thermal budget past which CMOS devices will turn into schmoo.
[a]: what’s the upper limit? As in, when does it not work anymore? For example, would it work at 100+ nm?
First, you need a wafer on which you can make a capacitor, which already means an SOI process, and SOI wafers.
The lowest nodes with SOI available to mortals are 40nm, and 14nm on GlobalFoundries, but god knows how one gets GloFo to collaborate on that.
Then, you need CMOS device which has enough thermal budget to survive both own, and DRAM creation.
Third, I think on-die DRAM will only make sense when it wins over SRAM. DRAM cells cannot physically go smaller than the minimal size of a trench capacitor. I believe at 5-7nm nodes, 6T SRAM will already be smaller than a reasonably fast eDRAM per area.
We know that IBM's Z15 is a 14nm FinFet chip, and it has DRAM on board, with them probably somehow doing DRAM first.
As you said, I'm not sure about the density part. Unless it's completely done in BEOL, I don't see designers trade precious chip real estate for memory (unless pin or power-limited, of course).
What do you think on FRAM vs. next generation MRAM?
Well, hafnium can be used to make ferroelectric crystals, that are necessary for ferroelectric memories (FRAM). The most used ferroelectric material is PZT, which has lead, and is a nightmare for CMOS compatibility due to contamination issues, and temperatures.
It's a bit light on the details, but maybe I should point you towards the video that explains our project: https://www.youtube.com/watch?v=M8tL-nN7G-A
The most exciting part might not be the performance (though it looks good), but the way ferroelectrics can be used for new circuits (variable treshold transistors thanks to FeFETs). Hafnium has been used in gate oxides for a few years now so it's quite compatible with CMOS.
No word on latency though.
Depending on what you mean by "memory-on-chip" we've already seen this with AMD's Fiji (2015) & Vega (2017) line of GPUs which used on-package memory in the form of HBM/HBM2 memory ( https://www.anandtech.com/show/9390/the-amd-radeon-r9-fury-x... and https://www.anandtech.com/show/11717/the-amd-radeon-rx-vega-... ).
It was incredibly fast, but also very expensive and limiting in SKU configurations. The resulting 16GB SKU for the Vega 56/64, for example, made basically nobody happy. It was too much for gamers, who then didn't want to pay money for something that didn't help, and it wasn't enough for the professional crowd, who were getting used to 24GB offerings from Nvidia.
> Actually isn't that already the case for mobile CPU's?
Nope. They "just" replace the slot with solder more or less. It's still externally packaged DRAM modules.
I see AMD's effort as a way to sidestep the whole problem of putting memory and CPU on the same chip, by making separate chips and stacking them. It makes sense. You can get CPU packages with CPU + DRAM + Flash, but these are separate chips which are wired together inside the package.
E.g.
https://en.wikipedia.org/wiki/Package_on_a_package
The whole point of these systems is to avoid putting memory and CPU (and flash) on the same chip. AMD's version is smaller & more integrated than package-on-package but it still achieves the same goal: multiple chips.
You also don't want to run your CPU at 80°C, else the RAM will produce much more errors. (ECC is a must anyway, I suppose.)