1nm Breakthrough: TSMC, MIT and NTU Published on Nature
buzzorange.com
buzzorange.com
From what I gather from the article, didn't get the Nature paper yet, the novelty here is a bismuth deposition process that doesn't damage fine structures underneath it.
This is definitely one of the hard problems in semiconductor manufacturing and as stated, it is implied it allows for very fine lines (1 nm) for connecting elements on a chip. If they can do that in a commercial fab it would help with density, if they are really able to reduce connection resistance to "negligible amounts" then that would be really good for power dissipation.
It isn't quite clear why they are developing 2D. Planar fets must leak terribly at these sizes.
Silicon lattice step is ~0.5nm, so 1nm is at most 3 atoms. Current technology is definitely not there yet however we're getting closer. Very interested what marketing department will say after 1nm became old news
Similar how music did not change much in the last 20 years
The term "5 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density, increased speed and reduced power consumption.
It is an industry standard term for describing a process node which is quite different from marketing bullshit.
• 480p/480i, SD
• 720p/720i, HD
• 1080p/1080i, full HD, 2K*
• 2160p, ultra HD, 4K*
* actually refers to several resolutions with different aspect ratios, but roughly the same pixel count
But definitely there is nothing 4000 about it, it's 3840 by 2160, about 8.3 megapixels.
Just because all of the marketing departments choose to participate in this particular bs doesn't mean it's not pure marketing bs. That just means it's industry standard marketing bs.
How Are Process Nodes Defined?
https://www.extremetech.com/computing/296154-how-are-process...
> The numbers that we use to signify each new node are just numbers that companies pick.
By TSMC standards, Intel's 7nm is a 5nm process and Intel's 10nm is a 7nm process.
So it is not even industry standard marketing bullshit.
0.8nm. Something TSMC stated they intend to bring to market by 2030.
Yes it is marketing term. But I thought everyone should know that by now.
But past 500 pm, the distance between silicon atoms in the crystal lattice, it will become increasingly harder to ascribe any physical sense to it at all.
It's as if we had only one efficient oil well for the whole world. It's getting a bit hot.
Historically, wars were often fought about some resource with limited access.
LOL. China is Taiwan biggest trade partner and source of trade surplus.
And they can get US military hardware and latest semiconductor equipment tools as well.
there are limits, we're just not close to them.
https://en.wikipedia.org/wiki/Limits_of_computation
> when i read about 50MHz being the fundamental impossible to surpass limit
yeah i think the problem here is popular press writing
If you are talking about quark litography (which does not physically make any sense as af as I can tell), then you are still agreeing with the parent comment, there are limits but we still have a long way.
Do you remember what magazine that was in?
It's hard to imagine anyone thinking 50MHz was a fundamental limit to circuit design, or computers, in the 90s. I am very curious what their argument was.
The Cray-1 ran 80MHz in the 70s. http://www.openloop.com/education/classes/sjsu_engr/engr_com...
FM is faster than that and it's been around a long time.
Where did you read that? As a working EE through the 80s and until today, I never heard that claimed. Maybe someone, somewhere wrote that, but it would have been an extremely fringe opinion. Even at the time I think most people would have received that opinion as a crock of shit.
In practice the only real fundamental limit to how fast you can clock a processor has to do with the gate rise and fall times, which are in turn intimately coupled to how large those gates are (the main factor in determining their capacitance) and the resistance in the charging circuitry for the gate. This is essentially an RLC network where all of the dominant factors are parasitic. What the real practical limits are is as of yet unknown but you always have to keep in mind is that this is tech at the cutting edge and that what is impossible today may very well a breakthrough away from being common.