Most fpgas are exactly mini async srams used as LUTs. The old MachXO series I'm working on actually allows using the luts as 16x2 bits RAMS (synchronous, single port or pseudo dual port). It also integrates a d flipflop/latch, a couple of muxes and some carry logic in each cell to give a little more power/flexibility, but the main architecture is sram luts, flipflops and giant muxes at each input to do the routing