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Comment by bsder | Hacker News Reader

RTL2GDS from a library. Based on Magic. And an SoC that they saddle you with.

Basically--totally useless or, if I'm being polite, nothing a modern FPGA couldn't do a hundred times better.

The worst part is that you don't need a zillion transistors to build an interesting chip. However, you need to be able to do physical design of those transistors if you want to do anything that couldn't actually be done on an FPGA. (For example: See the MN3007 Bucket Brigade Delay that so many analog delay guitar pedals are made from. https://www.electrosmash.com/mn3007-bucket-brigade-devices)

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There is a large selection MPW services, if you want to make an analog bucket brigade device, it could cost as little as 500$ for a small batch of chips.

https://en.wikipedia.org/wiki/Multi-project_wafer_service

https://www.musesemi.com/shared-block-tapeout-pricing

https://towersemi.com/manufacturing/mpw-shuttle-program/

One might be able to hack a linear ccd into a bucket brigade device by using an LED to modulate a signal into the array.

You should design a programmable 2d transfer matrix with summing, it could do some cool analog processing, like a 2d bucket brigade with arbitrary flow.

Stay happy friend.

All of your examples require signing an NDA.

The only service that doesn't require an NDA instead has all these weirdly crippling requirements that no other MPW has: the bloated mandatory SoC, RTL2GDS, no direct access to the pads, etc.

It's really sad. They fixed the one big huge problem with the state of MPWs, and then obviously said to themselves "hey, we did too good of a job here, lets crap this up a whole bunch to counteract that."

Is it useless for first graders to learn to read, because they won’t be able to understand James Joyce?

Are students who design and launch cubestats wasting their time because they can’t possible compete with commercial satellites?

You managed to miss the point of this program completely.

This program allows students and hobbyists to design and produce their own custom silicon. For free. They learn a ton, they’ll make mistakes, they’ll be able to see how others are solving issues, they go through the thrill of actually making their own chips, they’ll be able to test and characterize the result.

Nobody, well, except you apparently, expects the result to be competitive with a state-of-the-art process or an FPGA.

The problem is that this system puts people in a very complex design process at the 130nm node with no tools for managing that complexity.

It's like teaching someone guitar on a $50 Walmart special. Yeah, it's sort of a guitar--but it won't stay in tune, the action is way too high, the ends of the frets are sharp, etc.

It's more likely to discourage someone than convince them to go further.

Even the simple designs I'm looking at are going to struggle because it's pretty clear they couldn't get accurate parasitic extraction.

What students need is what the MOSIS (https://themosisservice.com/) MPW service used to offer (and may still) with older technologies like 0.5um and 0.35 where you could estimate the parasitics by hand because the process was simple and the overlaps were small relative to the geometry. What even sillier is that E-Fabless supports the X-FAB 0.5um and 0.35um nodes which are a MUCH better match to this kind of MPW thing for beginners.

Or, we need Google to pull its head out of its ass and do something useful for a switch--ie either 1) develop the physical design tools people need or 2) pay for people to get access to those tools.

> However, you need to be able to do physical design of those transistors if you want to do anything that couldn't actually be done on an FPGA

Only if you don't care about power consumption or speed. Just having a hard implementation of something instead of on an FPGA can be a marked improvement. (that said I agree it would be much more interesting to be able to design more directly).

There are also some analog designs listed, like this one:

https://efabless.com/projects/52

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