A fairly large amount of work is required to re-map the design onto Intel standard cells, which are not compatible with others. This means entire backend needs to be re-done. It's very significant amount of work.
That, and 3-4 months for manufacturing and test between tapeout and power-on. Automotive silicon has different test requirements than your average laptop widget.
Why would they port them to use new standard cells? Why wouldn't they just use the existing physical layout artwork to make new masks (i.e. GDSII files)? Assuming a closely compatible process. Maybe that's the catch? Intel's existing processes aren't close to anything anyone else has? Not that I think 6-9 months is reasonable.
Because the layout depends on the process. And processes are different.
If it’s just standard cells, then it could go quick. Change technology library and synthesize. But if there’s process-specific IP (analog serdes, non-standard cells, etc), then that takes work. I presume most automobile chips are not leading node high-speed switches.