It seems like nobody is talking about this, could anyone shine some light?
And immediately, we see the problem about dropping to 10nm: that's literally smaller than the distance that photons vibrate on their way to the final target.
And yeah, 10nm and 7nm is a marketing term, but that doesn't change the fact that these processes are all smaller than the wavelength of light.
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So there are two ways to get around this problem.
1. Use smaller light: "Extreme UV" is even smaller than normal UV at 13.5nm. Kind of the obvious solution, but higher energy and changes the chemistry slightly, since the light is a different color. Things are getting mighty close to literal "X-Ray Lasers" as they are, so the power requirements are getting quite substantial.
2. Multipatterning -- Instead of developing the entire thing in one shot, do it in multiple shots, and "carefully line up" the chips between different shots. As difficult as it sounds, its been done before at 40nm and other processes. (https://en.wikipedia.org/wiki/Multiple_patterning#EUV_Multip...)
3. Do both at the same time to reach 5nm, 4nm, or 3nm. Either way, 10nm and 7nm is the point where the various companies had to decide to do #1 first or #2 first. Either way, your company needs to learn to do both in the long term. TSMC and Samsung went with #1 EUV, and I think Intel though that #2 multi-patterning would be easier.
And the rest is history. Seems like EUV was easier after all, and TSMC / Samsung's bets paid off.
Mind you, I barely know any of the stuff I'm talking about. I'm not a physicist or chemist. But the above is my general understanding of the issues. I'm sure Intel had their reasons to believe why multipatterning would be easier. Maybe it was easier, but other company issues drove away engineers and something unrelated caused Intel to fall behind.
It seems like the diffraction pattern of the "long" wave laser would give you exactly what you want on the chip... and if you are putting hundreds of chips on a single wafer, it seems like you might not even need to worry too much about ringing at the edges.
The only ways to defeat diffraction are reducing it with shorter wavelengths and compensating it with multiple exposures with different patterns in which light and dark fringes compensate each other: exactly the two general approaches (EUV and multipatterning) taken by the semiconductor industry.
In the far field with a narrow bandwidth coherent light source (i.e., a laser), the projected image should be the FT of the aperture. That limiting condition is sometimes known as Fraunhofer diffraction, and generalizes to arbitrary apertures (not just a single hole).
Consider a narrow-band laser incident upon a diffraction grating for example. It produces a single point (well, two or three points, mirrored across the grating), not the uniform smudge that you'd expect by naively adding up the diffraction patterns of a bunch of slits. You should actually try this experiment for yourself!
The only trick is that you need a collimated laser and you need it to illuminate the entire inverse-FT-chip-grating aperture at once.
This deck has some nice examples of multi-hole apertures on slides 20 and 22: https://www.brown.edu/research/labs/mittleman/sites/brown.ed...
As to why it's not just a matter of buying a bunch of ASML lithography machines and plugging them in: In addition to what the other replies have noted, there is so much complexity and precision required in a fab. Consider all of the challenges that would be involved with starting with a bunch of industrial robots, and trying to build a fully automated assembly line that manufactures cars. Then scale precision requirements up by many orders of magnitude.
Making a device at a specific technology node (e.g. 14nm, 10nm, 7nm) isn't just about the lithography, although litho is crucial too. In effect, lithography is what allows you to "draw" patterns onto a wafer, but then you still need to do various things to that patterned wafer (deposition, etching, polishing, cleaning, etc.). Going from "we have litho machines capable of X nm spacing" to "we can manufacture a CPU on this node at scale with good yield" requires a huge amount of low-level design to figure out transistor sizings, spacings, and then how to actually manufacture the designed transistors and gates using the steps listed above.
Could we simplify this roughly into "ASML makes the machines to shine light at the right nm, foundries makes the Silicon and packages it into an useful device, architecture designers give you the layout to etch" if my mom were to ask?
EDIT: More seriously though: https://www.youtube.com/watch?v=NGFhc8R_uO4
> Its pretty simple. We zap sand with lightning until it starts thinking for us.
I think I kept working the joke in my brain, and it was too brutally simple at first. And then I worked it over, and now it reads too complicated. Ah well.
I think I was overthinking the joke.
Here's a neat video where they use an electron microscope to actually compare the transistor sizes for Intel 14nm and AMD 7nm: https://www.youtube.com/watch?v=1kQUXpZpLXI