Intel's Ponte Vecchio Xe-HPC GPU Boasts 100B Transistors

https://cdn.mos.cms.futurecdn.net/BUsZ5EdKUcP8mWRKypTNB4-970...

When excluding ML... (because that's what Intel gave actual metrics on for Xe-HP)

41Tflops FP32 with 4 dies. For comparison, an RTX 3090 (arch whitepaper at https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/a...) has 35.6Tflops FP32, with a single die.

https://github.com/intel/compute-runtime

https://github.com/intel/intel-graphics-compiler

https://github.com/torvalds/linux/tree/master/drivers/gpu/dr...

It does effect ennormously, but everything is highly design specific.

The die size limits are not only yield related.

Power, and clock have stopped scaling few generations ago.

New chips have more, and more disaggregated, independent blocks separated by asynchronous interfaces to accomodate more clock, and power domains.

If you have to break a chip along such domain boundary, you loose little in terms of speed unlike if you did it right across registers, logic, and synchronous parallel links.

Caches also stopped scaling too, and making them bigger, also makes them slower.

Instead, more elaborate application specific cache hierarchies are getting popular. L1-2 get smaller, and faster, but L3 can be made to ones fantasy: eDRAM, standalone SRAM, stacked memory etc.

>Or am I off in thinking this approach maximizes yields?

This is absolutely the case here especially for HPC or high performance market where they are all previously served by large die size solutions. You can also use the best node for each tiles / chipsets. Example I/O die may use other node for lower power consumption while Compute die uses High power node to push performance. High Density node for SRAM, low cost node for simple function accelerator etc. You can now customise each part of the tiles/chiplet best according to your target power/performance/cost equation.

Now of course their are trade offs, Intel Tiles packaging (EMIB, Embedded Multi-die Interconnect Bridge) is expensive. And it adds tiny latency for not being on die. Although you could argue you saved latency for certain parts with it not being off a PCIE bus.

But this is very exciting. The best part is with this announcement that you can use Tiles and Chiplet from other foundries on Intel packaging! You could theoretically use Global Foundry ( or Samsung ) FD-SOI node for certain applications and still be on the same packaging. You can now truly mix and match to the maximum.

Not so good part is we are still limited by TDP design. And I dont see anything being done in the consumer / prosumer space.

Very small laptops with Intel Tigerlake are on level with AMD and Apple products. They have all the new IO bits (PCIe 4, LPDDR4x, Wifi6) and low power usage on 10nm.

If you wanted a bit more battery life, performance, or just want to try a fancier display upgrading could be nice.

We are long past the days of buying a new computer every couple of years.