What does the C++0x standardized memory model mean?
stackoverflow.com
stackoverflow.com
C++, for all intents and purposes, supported multithreading before C++11 via extensions and libraries that are vaguely similar to each other on different platforms, but you can never be sure that your multithreaded code will work when ported to another platform (see "volatile" keyword semantics in standard C++ as opposed to MSVC).
But now,
1. it's officially mandated, and
2. you have more tools in your concurrency toolbox (for example, compiler-independent atomic variables with the ability to fine-tune memory order).
The point here is that they're just putting this into the standard and requiring specific semantics. This works because all CPU vendors have settled on a more or less consistent way of doing this -- synchronization is mature technology, basically. But it presumably also means that some older uniprocessor architectures won't be officially supported.
Wise people threw up their hands and said, "I'm not a ninja, so I'll just use mutexes and coarse-grained locking, nothing tricky, and see if it's fast enough," and they were mostly fine. I think that's what most wise people will continue to do, and the people who will get the most use of out the new standard will be people who have very special performance requirements or who write high-performance concurrent libraries (such as container libraries) for mere mortals to use.
1. ABI is a set of rules for interaction between multiple code units (functions, translation units, libraries) running sequentially and calling each other, e.g. how arguments are passed to the functions, how return values are passed back, how exceptions are thrown and handled.
2. Memory model is a set of rules for interaction between multiple (potentially) concurrently running threads, e.g. how a compiler can reorder load/store instructions to main memory, which operations imply memory barriers.
In a sense, VLIW/EPIC was one of the only things IA64 was trying to do differently than existing architectures. The chips have a bunch of cool RAS features, but Power5-7 have most of those too.