New instructions in Intel's Haswell microarchitecture

Overview of the new instructions (cutted and pasted from the PDF):

AVX2 promotes the vast majority of 128-bit integer SIMD instruction sets to operate with 256-bit wide YMM registers. AVX2 instructions are encoded using the VEX prefix and require the same operating system support as AVX. Generally, most of the promoted 256-bit vector integer instructions follow the 128-bit lane operation, similar to the promoted 256-bit floating-point SIMD instructions in AVX. Newer functionalities in AVX2 generally fall into the following categories:

• Fetching non-contiguous data elements from memory using vector-index memory addressing. These “gather” instructions introduce a new memory-addressing form, consisting of a base register and multiple indices specified by a vector register (either XMM or YMM). Data elements sizes of 32 and 64-bits are supported, and data types for floating-point and integer elements are also supported.

• Cross-lane functionalities are provided with several new instructions for broadcast and permute operations. Some of the 256-bit vector integer instruc- tions promoted from legacy SSE instruction sets also exhibit cross-lane behavior, e.g. VPMOVZ/VPMOVS family.

• AVX2 complements the AVX instructions that are typed for floating-point operation with a full compliment of equivalent set for operating with 32/64-bit integer data elements.

• Vector shift instructions with per-element shift count. Data elements sizes of 32 and 64-bits are supported.

These are extremely interesting instructions. It's worth noting, however, that things like gather/scatter live and die by the quality of their implementation. I would hope that these are considered worth delivering high-quality implementations, but let's just say that Intel has occasionally been known to deliver complex instructions that are all but useless due to poor latency and reciprocal throughput. SSE4.2, I'm looking at you.

I suspect that for these ones, it's going to be good - this looks too fundamental to the sorts of changes first described in Larrabee programming guides. The hope is that many of these functions (conditional loads, scatter/gather, etc) will allow a much larger proportion of loops to be parallelized than is currently the case. Obviously not everything is amenable to parallelization due to serial dependencies, but having scatter/gather to do multiple load/store stuff makes it a lot easier.

I think it is interesting the extent that this seems to be converging on some of the stuff in Larrabee - is the game plan to converge type of cores with GPU functionality so the difference between CPU/GPU cores is provisioning and access to some GPU-specific canned functionality for traditional T&L operations?

Overall it's like a wet dream for bit-bashers. PDEP? PEXT? Byte field extract? Scatter? 256-bit integer SIMD? I was almost too excited to speak when I first skimmed this (moderated somewhat by the 2013 release date and lingering concerns that some of the better insns will have latency 8 and reciprocal throughput 5 or something disappointing like that).

Wow, I can't wait to play around with PDEP and PEXT instructions.

These days it's the ARM instruction set I care about. Strange how fast x86 dropped off my radar.