Not sure if the checks of all loads are done at instruction retirement, but yes they are done after the (speculative) execution of the load.
We can also talk about the Store-to-Load Forwarding involving a partially check physical address, exploited by the Fallout attack, which is an optimization patented by Intel since 2006 [1].
All these Intel optimizations are old, and sometimes patented (which reduces the chance that IBM, ARM or AMD will do the same) and are totally valid and safe as long as it's assumed that it is impossible to recover data used during the speculative execution.
The recovery of this data becomes possible only when the side channel Flush+Reload is discovered in 2014 [2] (which originally didn't target speculative executions). It is only 3 years later that Meltdown attack use Flush+Reload as a covert channel to exfiltrate data during speculative execution.
It seems to me that this timeline shows that it was not possible in 2006 to anticipate this issue. So it's not just a lack of education.
Perhaps a lack of security research at Intel to continuously challenge their optimizations?
But please note that there is no theory to simply determine whether these optimizations are a good idea or not.
Criticism is easier afterwards when you know how the attacks are produced. But in 2017 this type of attack was something new.
That said, some of Intel's responses to the flaws (partial correction of vulnerabilities, lack of dialogue with researchers, etc.) are very worrying and I think these criticisms are much more legitimate.
[1] : https://patents.google.com/patent/US20080082765A1
[2] : https://eprint.iacr.org/2013/448.pdf