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Comment by rayiner | Hacker News Reader

I don’t know how this “memory on the SOC” thing became a narrative. That isn’t responsible for any of the M1’s performance. Apple isn’t using anything fancy like HMC or HBM that can’t be done with off-package memory. It’s a regular 128 bit memory bus and standard LPDDR4x (at the top standard frequency), with slightly higher memory latency than Intel and AMD. Pretty much any HEDT x86 system has a more impressive memory system.

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>I don’t know how this “memory on the SOC” thing became a narrative.

Yes it has been spreading like plague. And I had to post something similar [1] not long ago. And many more before that.

The M1 could have an Off package Quad Channel DDR4 Memory and still be as fast. The performance improvement ( from a memory perspective ) is coming from Same Memory Address Space and other similar optimisation.

[1] https://news.ycombinator.com/item?id=26225007

Going off package will at the very least increase power dissipation. Exiting a package, going across a PCB, and entering additional packages will increase capacitance significantly as well as increase resistance and inductance. This will impact performance. If the increased capacitance does not change actual operating speed, then the buffers are supplying more current to overcome the capacitance, not to mention the potential ringing and other undesired effects from the additional parasitics. There is a penalty for going off the SOC. It is not just a narrative, it is physics.

The same memory address space choice is of course important, but its performance and power envelope is impacted by the SOC vs. separate package choice.

The combination of M1 performance and low power has happened due to a series of choices made by Apple. Forgoing user configurability and fixing memory choices at manufacture while using SOC tech made mainstream by the phone industry is one of those impactful choices. There are of course several other important choices, but it is incorrect to discard this choice as non-impactful.

If I understood the parent comment, isn't it more about shared CPU/GPU memory? This is something different which M1 has in common with game consoles and smartphones but not traditional PC's, isn't it?

It's exactly same thing Intel and AMD have in their CPUs with integrated GPUs

no it's not the same. "Shared" means different things.

In M1, the GPU reads directly from memory written by the CPU.

In Intel/AMD, the data has to be copied from the CPU's address space to the GPU's. "Shared" only means there aren't separate main and graphics memory chips/banks. But said shared memory is segregated.

This document has something about Intel's UMA with zero copy buffers (not sure how relevant):

https://software.intel.com/sites/default/files/managed/db/88...

>> But said shared memory is segregated.

Uhm, as a games developer working on consoles.....no it isn't. You can do it like this if you wish, but generally the entire address space is accessible from either CPU or GPU. Maybe it's implemented like this on PC, but at least the architecture design on X1/XBS/PS4/PS5 allows both reads and writes from any area of memory by either cpu or gpu.

On pc by default the memory for the iGPU is a dedicated segment of RAM. There are probably tricks to read from each other RAM but not integrated like Apple has done.

It memory on a SiP.

Taking a quick look at an i9 9900 ($382 for chip alone) it supports DDR4-2666. i9-10900T runs at 2933 - $400 for chip alone.

Apple is running their stuff at 4100 or something. So that looks faster. And the mac mini costs $700 including the insane apple margins?

Can you spec out the $700 machine on pc parts picker that shows that the M1 is nothing special? One with faster or equivalent memory.

Calling the M1 and $700 machine a HEDT?? Huh? Apple is going to sell these things by the truckload.

My RAM on my 8700K system is running at 3200 mhz (XMP I). I imagine the 9900 can do at least that.

Using XMP may void your warranty: https://community.intel.com/t5/Processors/XMP-Warranty-void/...

This may have changed since then (Mid-2020). Gamers Nexus have done an undercover sting where they found it was possible for a support agent to reject a warranty request on the basis of XMP: https://www.youtube.com/watch?v=I2gQ_bOnDx8&t=1155

The i9’s slow supported memory is a product of that being Intel’s 14nm line which uses the same architecture released in 2015. The 10nm core chips use LPDDR4x, just like the M1. The $999 Surface Laptop 3 uses it at 3733 MT/s, just a bit slower than the M1: https://www.anandtech.com/show/14933/microsoft-announces-sur.... That speed of memory is supported on the lowest end 10nm mobile i3, which appears in sub-$300 NUCs available since 2019.

The M1 is a great chip, but that has nothing to do with the location of the memory. LPDDR4x-4267 is a standard memory type. Kudos to Apple for using the highest commonly available speed bin, but it’s a standard speed bin for that type of memory.

You claim it’s common but I haven’t seen that speed out there a lot. And def not in a package close to apples.

It's very common for high-end ultrabooks. Just look at the XPS 13 it runs at 4267. https://www.dell.com/ph/p/xps-13-9310-2-in-1-laptop/pd?ref=P....

exactly the same as the Apple M1. It's just the most common high-end memory speed currently nothing special about it.

Most i9 9900 chips will happily run DDR4-4266 as well. The reason Intel only lists DDR4-2666 has to do with JEDEC standards and overclocking reasons.

Also note frequency is only part of the whole picture. CAS latency is important as well, which is much higher with Apple.

I'd say that having massive low latency caches on die plays a larger role.

>On the cache hierarchy side of things, we’ve known for a long time that Apple’s designs are monstrous, and the A14 Firestorm cores continue this trend. Last year we had speculated that the A13 had 128KB L1 Instruction cache, similar to the 128KB L1 Data cache for which we can test for, however following Darwin kernel source dumps Apple has confirmed that it’s actually a massive 192KB instruction cache.

That’s absolutely enormous and is 3x larger than the competing Arm designs, and 6x larger than current x86 designs, which yet again might explain why Apple does extremely well in very high instruction pressure workloads, such as the popular JavaScript benchmarks.

The huge caches also appear to be extremely fast – the L1D lands in at a 3-cycle load-use latency. AMD has a 32KB 4-cycle cache, whilst Intel’s latest Sunny Cove saw a regression to 5 cycles when they grew the size to 48KB.

https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de...

That cache is that big because the decode and ROB are so wide. If AMD or Intel's current designs widened the L1, it wouldn't make a difference. In fact, AMD reduced L1 cache size from 64k to 32k from Zen 1 to Zen 3.

x86 needs to find a way to scale decoders without blowing the power budget. Given that the decoders are already bigger than the integer units, I suspect that will be a hard thing to do.

I get crashes with XMP, usually right at worst possible time on a zoom call where I am presenting! And saying users should overclock just seems weird, apple works out of the box.

For whatever reason, the overall memory system on the M1 systems just seems better than intel. I really wish I could follow more details from on-die cache to how memory is actually loaded / unloaded to speeds, but every time I've looked at it a little it just seems the M1 / Apple are doing it better across the whole stack.

Performance per Watt. Reducing the trace length makes it possible to get high frequency RAM working with acceptable power consumption. How many other ultrabooks clock their RAM at 4266MHz?

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