RISC-V is ready to take on Intel and AMD
datacenterknowledge.com
datacenterknowledge.com
No, it's not.
But it's closer than you might think.
The SiFive U84 and Alibaba XT910 cores are at about the same place as ARM was five or six years ago with the A72 and A73.
The U84 was formally announced 18 months ago, which means at that point design was complete and it was successfully running Linux and in particular the SPEC benchmark suite in an FPGA. That's when a company starts to take orders from customers who want to put it in an actual chip. The way these things work (at least in non-COVID times) the first such chips will probably hit first silicon in 6 to 12 months from now.
There are reports that the XT910 is actually in production use in Alibaba's data centre.
So RISC-V is about five or six years behind ARM. But five years ago it was 20 years behind.
Once the RISC-V BitManip and Vector extensions are ratified later this year (and Crypto soon after), RISC-V will be fully ready to compete with Intel, AMD, and ARM in terms of instruction set.
What remains then is for someone to invest the necessary few billion dollars to design a high performance core and SoC, along the lines of the Apple M1.
Not many companies have the financial means to do that. No one else in the ARM ecosystem is likely to do it any time soon -- including ARM themselves. RISC-V is pretty close to catching up to the cores available to Samsung, Qualcomm, Amazon etc.
If I had to guess, I'd say the most likely companies willing and able to make the investment to get a RISC-V "M1" and challenge Intel and AMD would be Alibaba and maybe Huawei.
There is no technical reason why not, only money.
How feasible do you reckon it would be, for a group of some sort (maybe consortium?) to do it instead of a "someone"?
Am thinking that with the Open Source nature of RISC-V, it might enable more co-operative methods of development, as happens with software.
POWER also has a code size problem -- it's just much larger than x86 and Aarch64 (very similar) or Thumb 2 and RISC-V (also very similar and significantly smaller than the proceeding two).
A couple of decades ago no one thought that was a big problem but now it is, not only because you need a bigger more power-hungry L1 cache, but also instruction fetch bandwidth from L1 is now one of the biggest energy users in a CPU core.
I think RISC-V has potential for servers if it can match the performance of x86 and power of ARM. Perhaps we'll see some trickle-down from HPC.
For custom SoCs, RISC-V seems like it might be more appealing than paying for an ARM IP core.
For researchers, students, and hobbyists, RISC-V is great, because it's free and open source and can run on an FPGA.
Pretty much any modern RISC CPU could be reasonably easily modified to run RISC-V code. An arm64 one is the obvious candidate. The ZERO register needs to be changed from reg 31 to reg 0 and a whole bunch of addressing mode stuff can be removed. The you need to either add support for RISC-V's "compare and branch" instructions (and rip out the condition code support) or else split the RISC-V instruction in to two arm64 ones (cmp then branch).
AMD could do the same with Zen3, but it would be a bigger job and a lot more would need to be ripped out.
We're still in the "overestimated" part right now with respect to RISC-V.