It means the ML algorithm can propose designs that do well on the objective function (e.g. improved runtime), but can't actually be constructed. They give the example of designs that have more memory than can actually fit on the chip.
So the problem is that there is no software mapping, which I understand to be the mapping of compiler instructions to the underlying hardware. It looks like I'm missing something. Is this the same as saying that the hardware design is not feasible?
They also have a way to run that hardware in a simulator and see how quickly it could train some network.
The ML optimization problem is to come up with a bunch of constants which performs well, but also compiles into a manufacturable chip. Clearly setting the clock speed to 9999Ghz isn't that...