Hacker News Reader

Comment by lmilcin | Hacker News Reader

> Microprocessor based Network Time Protocol (NTP) servers suffer from a large amount of timestamp jitter, due to the hardware and Operating System (OS) being shared among other applications.

So instead of configuring Linux correctly and dedicating a core for your NTP you have created custom hardware. Congratulations, now you have two problems.

I have been working on algorithmic trading and it is not that hard to reliably (like 100% of the time) respond within couple microseconds.

You will never notice it, though, because your network will introduce way more variability. This is especially the case with NTP which usually is a single box shared between large number of servers throughout your network.

View on HN

> I have been working on algorithmic trading and it is not that hard to reliably (like 100% of the time) respond within couple microseconds.

As someone who works in the flight test instrumentation industry (that primarily uses PTP rather than NTP), my first thought was "is a couple of microseconds supposed to be good?". With PTP, I usually achieve RMS offsets of < 50 nanoseconds over gigabit Ethernet.

I sort of agree with your point in that it's probably pointless implementing NTP inside of an FPGA, but I'd like to extend it further and say that if you really care about accurate timing, you should be using PTP rather than NTP anyway. In that case, an FPGA solution makes much more sense. However, in the systems I've worked with, the FPGA only implements a few pieces of core functionality - like the frame time stamping and the numerically-frequency-controlled clock. The actual protocol is usually implemented in software, except in the case of transparent switches.

That said, most modern NICs have PTP hardware, but you still usually need some external logic to actually use these synchronized clocks.

On a "normal" box the time is usually combination of various sources neither of which was really designed to provide accurate, sub microsecond, absolute time. (That except possibly for this "PTP hardware" in NICs that I don't know anything about)

So even if you somehow devise a piece of hardware to pass the accurate time to the operating system, there would be no way to track it accurately.

Now, I think that really accurate absolute timing on machines isn't really that critical. For example, for consistency protocols usually it is enough to provide guarantee of 1s around true time.

For algorithmic trading we were mostly interested in responding as quickly as possible to the event that came from the stock exchange. The packets always came with a known delay and the timing wasn't all that important except for debugging. Everything was done on a single box (so no need to synchronize with anything else) and even on that box the events were processed such that there was no need to coordinate with other threads, each thread just consumed, processed and published results.

Most Intel 10 gigabit adapters support PTP.

It's just about inserting the exact time the frame will be sent into a sent frame, and noting the exact time the frame is received. All that's left is a small amount of clock jitter and cable delays.

High end switches support PTP themselves so you don't need to worry about queueing delays, but you don't need a switch that supports PTP to get high resolution, low jitter, low uncertainty time-- at least on reasonably sized networks that are usually not saturated.

There are many algorithmic trading applications that rely upon high quality time derived from a single coherent source, along with telecommunications, control systems, instrumentation, etc. And there are other distributed systems approaches where true ordering is nice: yes, you can provide ordering within a system of dependent events using a Lamport clock, vector clock, etc, but without high quality time you can also correctly sequence causally related events originating outside your tightly coupled system in many use cases.

That said: PTP relies on a tightly coupled master and realistically is intended for a tightly coupled, hierarchal system. NTP is a better "internet" time protocol-- lots of logic for clock precedence, averaging of multiple sources, slower control system, etc.

A lot of intel 1G adapters do too, likely including the one in your laptop.

  $ lspci -s 0:1f.6
  00:1f.6 Ethernet controller: Intel Corporation Ethernet Connection (4) I219-V (rev 21)
  $ sudo ethtool -T enp0s31f6 
  Time stamping parameters for enp0s31f6:
  Capabilities:
   hardware-transmit
   software-transmit
   hardware-receive
   software-receive
   software-system-clock
   hardware-raw-clock
  PTP Hardware Clock: 0
  Hardware Transmit Timestamp Modes:
   off
   on
  Hardware Receive Filter Modes:
   none
   all
   ptpv1-l4-sync
   ptpv1-l4-delay-req
   ptpv2-l4-sync
   ptpv2-l4-delay-req
   ptpv2-l2-sync
   ptpv2-l2-delay-req
   ptpv2-event
   ptpv2-sync
   ptpv2-delay-req

Yup-- I didn't know the prevalence so I didn't say.

You're wrong though-- there's no ethernet adapter in my laptop ;)

Touché :D

(sadly, 802.11 timestamping on wifi is very fringe...)

It's hard to do PTP reliably over WiFi since the symmetry in both directions (client<->ap) isn't really consistent. It _does_ sort of work though.

It could be made to work fairly well with hardware / driver support. Timing information of frames is known rather precisely, and delay spread is <100ns in most environments.

> dedicating a core for your NTP

Heh as soon as I read this I thought "algo trader?". If you don't mind me asking outside of trading how often do you see systems seriously manage jitter (specifically I'm thinking about interrupt management). I'm in HPC and whilst some such management is present it seems seldom thought about.

Heh, I already thought somebody will point it out.

See, they decided to create custom hardware just to do NTP. How is instead dedicating a single core a worse solution? Setting dedicated core is basically configuration detail.

There are no gains from custom hardware as network variability would mask them. If you want really good time guarantee because having right time is critical for your application, you put atomic clocks in your servers as one well known company does.

Also, it is customary to have dedicated machines for various functions. You would not normally want to mix some different types of loads that conflict with each other, for example high security with low security, high throughput with real time, etc.

You could just configure a single machine dedicated to NTP (which is customary), but instead of sharing cores between OS and NTP (and introducing jitter) you can have separate core for the OS and separate for NTP so that NTP can work undisturbed.

So if you maintain an NTP instance and have problem with jitter and you red this article my hint is: don't set up custom FPGA to fix your problem, just dedicate single core on a machine you already have and you will get as good results as you can.

Oh I wasn't meaning specifically in the context of NTP, just generally.

> Oh I wasn't meaning specifically in the context of NTP, just generally.

So you decided to just answer with a generalization without regard for the particular case of NTP?

Are you frequently building custom hardware when default OS settings do not suit your needs?

Linux has a lot of configuration potential. It is wise to explore and understand various knobs available before you decide to complicate your life and build something very complex that could easily be replaced with a one line shell script.

Have you perhaps mixed up my comment with this one https://news.ycombinator.com/item?id=26152783?

I was just asking about your thoughts of how outside of trading jitter is seldom considered. I appreciate it's off-topic from the actual HN post but I was curious given your experience in trading.

> How is instead dedicating a single core a worse solution?

It is pretty much guaranteed to perform worse, if that's what you mean. Is it worth the effort and extra complexity? Probably not.

The timestamping jitter with an FPGA would probably be on the order of tens of nanoseconds while we're talking microseconds with a software solution.

> There are no gains from custom hardware as network variability would mask them.

I _think_ multiple cascaded jitters in a system add with the square root of the sum of squares, so there would still be an improvement.

Consider a system where you had 10 microseconds of inherent jitter, then you added another 10 microseconds on top of that. The total is not 10 microseconds - it would be 14.

> Is it worth the effort and extra complexity? Probably not.

That's pretty much definition of a worse solution.

Not necessarily when it comes to something like HFT, where they do things like run point to point microwave links to reduce latency by microseconds.

The precision achievable with FPGAs is well beyond 10s of nanoseconds.

The high rate transceivers are used with capacitative dividers or internal signal propagation delays defining the reference intervals for time to digital conversion in extreme accuracy applications, these and similar approaches yield precision to picosecond scale and beyond.

Right, but Ethernet timestamping usually occurs on a symbol or byte level inside the MAC, so for GigE, you're looking at 8 nanoseconds per symbol. This could be improved by oversampling the symbols, but at least with GigE, there's (I think) 4 cycles of uncertainty each time the link comes up due to how the clocking agreement between master/slave is established. It's also somewhat difficult to run large counters faster than a few hundred MHz inside of an FPGA. I've worked with systems that use two different clocks - one small counter for Ethernet timestamping, and another main clock, with a periodic latching between the two to correlate them, but it's uncommon.

There's also the fact that most PHYs operate by having a FIFO with data being clocked in and clocked out on different clock domains. The way I understand it, the PHY FIFO fills up half way, and only then does it start draining into the MAC. This is to allow for oscillator frequency errors between each device. This is also why there's a maximum frame size and max oscillator tolerance specified for Ethernet - so that this FIFO doesn't under or overrun before the entire frame is received.

I think sync-e can improve this quite a bit.

Of course, FPGAs themselves are capable of much tighter timings, but in practice, it's usually implemented this way.

The approaches I am referring to are indeed oversampled and occur in a "bump in the wire" or on a parallel data path.

Moreover, the oversampling occurs at a much higher frequency than the maximum counter frequency of the FPGA -- each clock period is divided into a fractional offset from the rising edge by the capacitative divider or delay line.

It is not uncommon at all for dedicated PTP/NTP hardware to implement synchronization and timestamping in this way, even commodity NICs supporting hardware timestamping often implement it on at least a parallel data path.

NTP is hilariously insufficient for HFT, we have far better protocol around: PTP.

https://en.wikipedia.org/wiki/Precision_Time_Protocol

I'm aware, I was talking about jitter in general.

Jane Street has an interesting podcast on this very subject: https://signalsandthreads.com/clock-synchronization/

The uncontrollable and unobservable SMM interrupts of most modern CPUs add sufficient jitter to the reference clock sampling that there is no correct configuration.

You generally must use an FPGA or appropriate DSP/microcontroller to achieve precision beyond ~10s of nanoseconds, which is entirely achievable even with NTP between hosts that have low contention 10+Gbps per transceiver lane interfaces / properly configured DCB/QoS so the time synchronization packets always egress without delay. PTP can, of course, achieve even better precision.

Round trip time / transmission time ("respond within couple microseconds") are irrelevant, it's a rising or falling edge feature of the packet burst which timestamps the sample and the interval between these samples that's used to train the clocks. This can be accurate to within femtoseconds at the extreme.

Let's say you get FPGA and then what? Where are you going to use that signal? On a server that has "uncontrollable and unobservable SMM interrupts"?

Sure, why not?

It's going to offer an incremental improvement in accuracy for the server's derived clock when the reference clock is not affected by that and other sources of jitter.

Beyond the accuracy, the hardware is significantly cheaper and more efficient than a server with a general purpose x86 CPU.

For a dedicated network reference clock, an FPGA or ASIC solution is simply better in every measurable way.

It is more complex, to be sure, but the complexity needn't be your concern.

Yes, doing things fast is the unremarkable part. Doing things fast and synchronously over the network is the trickier one.

Reply on news.ycombinator.com