> RISC-V seems like it hasn’t learned anything from CPUs designed after 1991.
Never mind what RISC-V says about itself. Here is Dave Jaggar, a key ARM architect, endorsing RISC-V as state of the art in 2019: https://youtu.be/_6sh097Dk5k?t=51m10s.
Never mind what RISC-V says about itself. Here is Dave Jaggar, a key ARM architect, endorsing RISC-V as state of the art in 2019: https://youtu.be/_6sh097Dk5k?t=51m10s.
I'd love to see the result of a concerted ground-up creation of a hardware and software system that starts from scratch and leaves unresolvable legacy considerations to virtual machines or whatever.
Anyway, totally Off Topic, but thanks for what I'm assuming will be my watching that entire video!
The entire effort of supporting it and building the ecosystem will be hard to justify economically at these cost figures.
Mill on the other hand has a lot of interesting ground-breaking ideas that can potentially offer a 10x performance/watt improvement.
Many people have been recently in awe after experiencing the ARM performance improvements around 40% offered by the Apple silicon and AWS Graviton CPUs. Just imagine something offering a 10x based on a Mill design, I'd love to see it built one day and available on the market.
This has been tried often. (Thinking Machines, Multiflow, e.g., not to mention Itanium) I would love to see this too; I worked for a startup that tried to do this (vliw, no specex), and taped out with a working chip, after 6 months. Maybe the startup didn't have the right sales team, but they didn't manage to make any meaningful sales, the culture in the buyer's market is too conservative.
In the case of the company I worked for I suspect that part of the problem is that conservative buyers will look for excuses to say no, instead of excuses to say yes. One such example is that nobody would accept that you could move specex to the compiler, with the old "sufficiently advanced compiler" joke, despite the fact that they could prove that llvm was "advanced enough".
Sorry, couldn't resist a well-assembled pun.
Your post in interesting. I agree yet disagree. You got the context correct but he explicitly said 'it's the standard now for 32 bit general purpose instruction sets and it's got the 16 bit compressed stuff. Learning from the best still'.
Standard =/ state of the art but in this context, he's stating that learning from the best (state of the art CPU designs) is by learning RISC-V.
One doesn't say something is a standard and state of the art in one breathe, to somehow believe that they're doing something outdated or from 1991's knowledge base.
I think you're interpretation of his message would need to have further explicit statements from him to support your claim (that somehow 'state of the art' doesn't mean for CPU design, instead of just learning CPU design).
The listener would be better suited to follow @seedless-sensat's (and my) understanding because there is no evidence to the contrary of what we're stating. The speaker intended both (but if you can find evidence to support your different thesis, I look forward to investigating it further).