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Comment by userbinator | Hacker News Reader

Prevous attempts at taking a regular CPU architecture and turning it into a GPU haven't worked so well --- it's what Intel attempted many years ago --- so I'm not too optimistic about how this will turn out. Then again, the boring and uniform nature of RISC-V may be more suitable to mass parallelisation in a GPU than as a CPU.

The name is slightly reminiscent of https://en.wikipedia.org/wiki/File:RIVA_TNT2_VANTA_GPU.jpg

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FWIW, NVIDIA have been adopting RISC-V as the internal ISA for their GPUs: https://riscv.org/wp-content/uploads/2017/05/Tue1345pm-NVIDI.... It’s definitely a different architectural approach than described in OP though.

No, it's not the GPU ISA. Complex chips tend to embed management cores, for example to handle power management or various configuration operations across the chip. NVidia used a proprietary ISA (Falcon) for such cores, and moved to RISC V. But this is independent from the GPU ISA itself, which remains NVidia proprietary. So in the end, in their embedded SoC you can find (at least) 3 ISAs: ARM for CPU, NVidia proprietary for the GPU, and RISC V for NVidia management cores. And it's likely there are more, for example for audio DSP and other IPs embedded programmable units.

It's not the internal ISA of their GPU but of a CPU they use in their designs.

From what I researched, Falcon is used on nVidia GPUs for everything _but_ the graphics, for example to enforce a security model. But it's a start. Probably they will start using for other purposes as well, for example video encoders and decoders. I very much doubt though they will scutte their existing GPU architectures for RISC-V yet.

Every attempt to do what other people have failed at benefits from hindsight.

There's been one major success case: A64Fx and ARM SVE. The Fujitsu processor just recently took #1 in LINPACK, #1 Green500 (also the most efficient) and also #1 in HPCG (an alternative benchmark that GPUs traditionally suck at).

Its not a full GPU yet, but that A64Fx is clearly a powerful SIMD compute cluster, very similar to a GPU. It has succeeded where the Xeon Phi seems to have failed.

It's unclear that this particular project has learned from Larrabee hindsight. The graphics part of the GPU doesn't seem to be thought through at all.

That said, if the goal is to compete with existing GPUs for general compute workload, the graphics part is unnecessary anyway. That could work out, though calling it a GPU is a red herring.

The money is in general gpu-like compute, not in actual GPU operations.

Blending pixels is becoming less and less important in the power budget of mobile devices too.

And yet in-order blending is so much more power- and area-efficient with fixed function hardware support that, if your goal is to support graphics, especially for a mobile part, you'd be silly not to add it. The same applies to rasterization and a number of other similar things.

Again, this doesn't matter for a pure compute part. It's just not particularly clear from the article whether they're even aware of the distinction.

This doesn’t quite seem like that as the implementation of the instructions isn’t yet specified. Even if it is integrated, it can use dedicated VRAM and not have to use the CPU’s ALU.

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