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Comment by lwneal | Hacker News Reader

> Today’s state-of-the-art is five-nanometre chips (though “5nm” no longer refers to the actual size of transistors as earlier generations did).

It's refreshing to see this mentioned. I'm no semiconductor expert, but it seems weird to me that although node size is measured in a physical unit, nanometers, it does not correspond to any real measurement that exists [1]. Each transistor in a 5nm chip is actually between 28 and 36 nanometers in width. It's called 5nm because of a theoretical calculation based on transistor density [2].

If Tesla advertised a new "200kWh" battery, I would be very disappointed if it turned out that the battery only held 95kWh, but the marketing department had decided that improvements in the charging network have made it "like 200kWh" compared to earlier models.

[1] https://en.wikipedia.org/wiki/5_nm_process

[2] https://en.wikichip.org/wiki/technology_node#Meaning_lost

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Interestingly, there is one dimension that still tracks the node number fairly closely.

In fact, the node number has never referred to transistor dimension, but the length of the gate electrode. A transistor would typically be about 4 times larger than that.

The reason to refer to the length of the gate electrode is because that was always the smallest feature printed on the chip. And that is what defined the required resolution of the lithography process.

So, a lithography process with a resolution of 32nm would be able to print chips with 32nm gate lengths.

Much has changed, and now transistors are no longer planar, they are 3-dimensional fin structures (FinFETs). The gate length scaling has slowed down, and now is not the smallest feature on the chip anymore.

The smallest feature in a modern FinFET process is actually the with of those 'fi s' that form the transistor channels.

And as if by magic, they correspond pretty well to the node names, i.e. a 5nm process will have a fin width of about 5nm.

You will likely not find that mentioned anywhere, it's just a fun fact that I noticed as a VLSI technologist.

It's still a little disingenuous because most performance parameters are directly related to transistor lengths, whether finfet or not. There used to be a concept of "scaling" where you could roughly estimate that going from a 40nm process to a 28nm process, for example, would save you (28/40)^2 percent power. Finfet disrupted that to some extent, but it partly held true as physical lengths actually continued to decrease with node names. By now, though, it is generally understood that state-of-the-art process node numbers doesn't mean much in that regard.

I also just checked a handful of processes I have access to, and at least in these cases, the fin width doesn't scale with the technology name (e.g. 5nm and 7nm has 8nm fin width drawn in layout, and model indicates 27nm "width" per fin). This isn't much of a surprise to me, because foundries are just decreasing the number with newer generations of the tech, even if the lithography (the method by which features are etched into the silicon) hasn't significantly changed. For example, 3 generations of a single process were called 7***, then 5***, then 4***.

> It's still a little disingenuous because most performance parameters

That's your bias. To a process engineer the parameter that matters is what wavelength you are blasting the mask with and what size a feature it can create.

This is probably similar to the debate between management and engineers at Intel. As an outside observer who has never been near CPU design let alone process engineering - TSMC's nomenclature smacks of moving the goal post to claim a win. Despite the reality that from a process engineering standpoint decoupling the "transistor size" from the production node is an improvement and allowed TSMC to ship a technically superior process.

And also does it actually matter. It ultimately refers to some improved denser semiconductor process which is what the customer is buying.

These processes are not exactly standardised either it would be a major undertaking to take an architecture from TSMC 7nm to 5nm let alone moving from TSMC to Samsung, Global Foundaries or if at all possible Intel.

So essentially the 'node' size is the lithography process, not the chips you design with that process. You can't make a feature smaller than the lithography process, nor x.5 times as big as the resolution of the lithography. There will then be a bunch of parts of the chip that are just a little bigger or a little farther apart than they need to be.

Not unlike how there are pipeline phases that are just a little longer than they theoretically could be (because all of their neighbors have to line up with each other). If you can fix the bottleneck then everything else can shine, causing a magical, outsized improvement.

The node size never referred to the actual size of the transistors. Back in the days when CMOS scaling was simple, it referred to the half-pitch, half of the center-to-center distance of the Metal 1 lines. The gate length was roughly the same, usually. But scaling had to be changed starting in roughly 2003 because atoms don't scale; the joke was that transistors were no longer switches, but just dimmers, because leakage was an increasing problem. Designs could no longer be simply scaled, producing a faster clock cycle for free; they had to be revised, and a FinFET looks very different from a traditional FET.

To make further progress designs had to be changed, and things have gotten fuzzier. Processes from different foundries have different densities. Intel's process for a given node is denser than that of the big foundries like TSMC.

See https://en.wikichip.org/wiki/technology_node for more on this.

On the plus side, MT/mm^2 seems to be gaining steam as a metric. It removes one dimension of cheating and has the whole "bigger is better" thing going for it.

That's "mega-transistors" per mm^2?

Perhaps it would be better to go with "6502s per square millimeter" or something like that that would probably be a closer approximation of real-world density, since it accounts for wire routing and so forth.

SRAM density is sometimes used I think.

Today's chips have many more layers of interconnect than the 6502. Also the aspect ratios of transistors are different.

Not folksy enough. Just like we use Libraries of Congress to measure information volume, we should rate our chips in terms of AGC/mm^2

(Apollo Guidance Computer)

Well, I would be just glad that at least it's not AGC/sq in

A nice approach I'm hoping will gain traction when discussing density across different types of logic is the "LMC" metric, as put forward by some TSMC and Stanford folks: https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9063714

Improved semiconductor device density directly translates into benefits for more advanced computing systems— the primary driver for progress in semiconductor technology. Thus, we propose the use of the following three-part number as a metric to gauge advancement of future semiconductor technologies: [DL, DM , DC ], where DL is the density of logic transistors (in #/mm2), DM is the bit density of main memory (currently the off-chip DRAM density, in #/mm2), and DC is the density of connections between the main memory and logic (in #/mm2). As an example, today’s leading edge technologies that are published in the literature [15]–[17] can be characterized by [38M, 383M, 12K]. As another example, 3-D stacking of multiple logic and memory dies can increase DL, DM, and DC .

I love the idea of having that information readily available, but I don't think it will ever be a banner spec. Three numbers is two too many and who wants "density" when you can have "MEGATRANSISTORS"? I know, I know, but marketing is what it is and I think it's better to lean into it.

Of course, and I agree that marketing traction matters. I should have said this is an idle hope that some of these fancier metrics get published/leaked about TSMC/Samsung/Intel processes rather than that they become the metric. I do think MT/mm^2 or whatever is a strong candidate to become the thing. "megatransistors" is an exciting word.

>> "megatransistors" is an exciting word.

Not as cool as megaFonzies.

So is that going to be M as 1000^2 or M as 1024^2.

(still bitter about the whole GB vs GiB think caused by marketing people)

To be fair to marketing people, they were correct, weren't they?

Deciding that in your field you're going to redefine standard units and their abreviations is a bit lazy.

Should that be future-proofed and be per mm^3? I was under the impression that designs are becoming more three dimensional.

Maybe for memory, but I think it's too early for logic where heat transfer forces you to keep volume per surface area under control. Legitimate 3D logic will require a radically parallel compute model, probably something neural, and until we see what form that takes I think it's better to keep the metric 2D.

According to the Bekenstein bound, the maximum entropy in a given region of space is proportional to the area of a surface containing that space, not its volume so to really future-proof it, we should probably go with per mm^2...

Isn’t that still a very bad descriptor though, like relying only on clock speed to make a decision? Though I guess many people do; back in the day, I think AMD cpus were on par with intel CPU’s running 200MHZ faster. But all people saw was AMD 1.7Ghz and intel 1.9Ghz. The result, the AMD chips at 1.7Ghz were called Athlon 1900. Which is the same thing as the equivalent feature length for FinFet. The people in the know should actively be discouraging reliance on single dimension (frankly misleading) terms.

Similar story with audio amplifiers and "Watts." Also, I think that small gas engines like lawnmowers went through some kind of scandal related to their horsepower ratings.

Yes, some amplifiers would be advertised with nonsense like “watts RMS”. The concept of “watts RMS” makes no goddamn sense.

Actually in the US, the term "Watts RMS" specifies that the measurement is done according to the FTC Amplifier Rule. Now that rule has its own pro's and con's of course, but at least it's pretty definite. With all of these things, there's a corresponding European rule as well.

Whether the measurement method is appropriate to your use of an amplifier is of course anybody's guess.

Considering that the load impedance of audio amplifiers isn't always the same, it'd be a bad idea to measure output voltage in terms of gain compression points/clipping/max continuous.

I agree the term "RMS" is kinda miss-appropriated, but it's short and tends to understood as something reasonably close to what it's actually about.

How about vacuum cleaners with HP? I guarantee that there isn’t a 3HP motor that works on a 120VAC (RMS) 15A (RMS) circuit.

A friend worked on a blender. The wattage number was derived from the inrush current when first turned on.

To be fair, that might be the current draw in stall.

They are basically the same quantity - the motor doesn't care if the rotor is stopped because it's physically locked in place, or just because it was previously not running.

I don’t think so. Attempt the opposite experience: If you turn the motor, electricity comes out. So I don’t know what is the draw when stalling but I guess the draw must vary a lot even inside a north/south cycle.

In fact, the draw varies enough during the cycle that it’s a well known method in industrial ecology to put a condenser on a 60Hz motors when the supply is 50Hz. So there must be a visible cycle.

The magnetic behavior of the windings can depend on this, though. A good example would be a toroidal transformer, which tends to have a high inrush current, even if the output is open circuit.

I’m glad I don’t have that blender. :) (I’m the proud owner of a blender with a bona fide brushless motor. I don’t know specifically what type, but I suspect the inrush current is quite low. It also outputs considerably more power than most brushed motors can probably manage for any length of time.)

edit: The product blurb says it’s an induction motor. The nameplate says 1000W. It would be fairly straightforward to estimate the efficiency by blending a known amount of water and measuring the temperature change over some period of time.

No, that's just shitty vendors being shitty.

Accurate RMS can easily be calculated and advertised. Check out Steve Meade and his tools/videos if you're unaware.

Most prominent brands just choose to market absolute bullshit numbers - people who know what they're actually after know how to find the brands who publish real numbers.

Yeah I remember when they switched from RMS to PMPO. Overnight a big speaker system went from 50-100W to 2kW or something ridiculous.

I thought the 5nm referred to the smallest dimension in a FinFet device. Specifically, the fin: "In theory, the finFET hits its limit when the fin width reaches 5nm, which is close to where it is today." [0]

https://semiengineering.com/5nm-vs-3nm/

I feel that stuff like this has a long history in engineering. It's like how TVs are in the 55 in "class", or a 2x4 is actually something like 1.75x3.5 now.

I don't think we should limit to just engineering; you see this stuff in media, politics, finances, statistics, etc. Anything that is not well understood by the public at large is ripe for misuse.

2x4s are 2x4 before they're seasoned, though. The lumber is dried after dimensioning and shrinks as it loses moisture. But we still label it by the original dimensions because lumber is priced by the board foot (which is itself a weird archaic measure) of the lumber when it was cut.

For comparison, sheet goods aren't priced this way. A 3/4" sheet of plywood really is 3/4", because the plywood was manufactured that way and as a manufactured product there is no seasoning.

You're not being ripped off because a 2x4 is actually smaller. A sawmill had a tree, and they cut off a hunk of that tree, and they charge by how much wood they cut off. The dimensions of that piece of wood changed after they cut it (which in and of itself is a service they provide - it would be a hassle if you had to buy green lumber and dry it yourself).

2x4 in old houses will measure 2x4 and is "rough cut". Modern milling will turn rough cut true 2x4 into the clean cut "2x4" you use today by running them through additional planing process. I don't think any shrinkage is significant though.

3/4 plywood will measure less than 3/4.

3/4 inch plywood is usually actually about .7 inches

Does this vary more depending on the plywood grade, maybe? I have some shelving I made from AB birch, and it looks pretty close to .75. Maybe 1/64 scant. (Although I don't have calipers handy and just used a tape measure, so I'm not being super precise.)

Lots of plywood, especially birch, is metric-sized. You might have 18mm plywood on your hands, which would be about 1/32 under 3/4 inches.

The plywood I often buy at a big box home store is labeled as 23/32" (0.71875" or 1/32" less than 3/4") and it is actually that thickness. I don't recall seeing any 3/4" labeled plywood though.

I work in sawmill technology. Way back in history 2x4 were cut to 2" x 4". In a modern sawmill 2x4s are never cut to 2" x 4". They are cut to a thickness and width such that given saw deviation, and variable drying shrinkage nearly all boards will cleanly plane down to 1.5" x 3.5". The exact target dimensions will depend on how well the mill can control their saw deviations and the statistical range of shrinkage they expect for the wood they are cutting. Reducing dimension targets by controlling saw deviation and understanding drying shrinkage is a big part of sawmill efficiency and profitability.

Fair enough, thanks for those details. Out of curiosity, do you know roughly what the target dimensions usually are now a days? I'm curious how much the efficiency gains are.

It's interesting that lumber kind of looks like shrinkflation (what the comment I was originally responding to suggested), but it's more that technical improvements have allowed producing the same finished product with less input material. But we still label the stuff by the amount of input material it used to take for historical reasons, which at a glance looks like shrinkflation.

https://en.m.wikipedia.org/wiki/Lumber

And what's is worse is how hard it is to know the true size of everything you find in stores in the USA. The same applies to pipes of all types. But even things like a drawer slide is often not the advertised length. Saw blades thinkness is converted from 2.5mm to whatever the closest inch the salesperson felt that day.

From having spent quite a lot of time in big box stores in France and the USA. I can tell you that in the USA 3/4" (19mm) can be anything from 16mm to 24mm.

In short almost everything is built in metric and the USA likes to pretend it's not and gets confused by rounding up randomly.

"Building" (or worse "designing") a computer is assembling lego bricks. Serious language inflation.

Yeah, these casuals think they're building a computer when they're really just sticking ICs together. If I was building my own computer, I'd do a real DIY build and start by creating the universe.

It's not new: CRT TVs and monitors were marketed by the size of the tube, rather than the size of the visible part (the screen itself).

And a 16oz iced coffee from Starbucks doesn't contain 16oz of liquid!

Funny, but Tesla actually stopped advertising battery sizes when the model 3 came out. It's actually a bit of work to find out (answer: 54 or 62 or 75 kWh)

True, and this is precisely why they did it - this way they reap the benefit of any efficiency improvements. If their tech improves, it costs them less to build a "300 mile" car, rather than the buyer simply getting slightly more miles out of a 90kWh car.

Remember when Mercedes E230 meant 2.3 litre engine? I feel this is similar. Indeed a long history as another commenter points out.

Yup. Similar with BMW. 330 meant 3 liter engine. Now it’s all the “equivalent“ game.

Mine's a 325i, that actually has a 3L engine.

230 deci-litre?

230 centiliter

> Each transistor in a 5nm chip is actually between 28 and 36 nanometers in width. It's called 5nm because of a theoretical calculation based on transistor density

So, TSMC is not really that far ahead after all? 28 nm is like a decade old now?

This sounds like women’s vanity sizing. Size 6 is now Size 0.

GHz would be a better analog of KWh. Anyone that isn't an electronics engineer is not qualified to talk about '?nm' technologies

> Anyone that isn't an electronics engineer is not qualified to talk about '?nm' technologies

Jesus, this is the height of arrogance...

Wendell Wilson isn't qualified to talk about this?

Linus Sebastian isn't qualified to talk about this?

Dr. Ian Cutress isn't qualified to talk about this?

I would listen to all three of those before I listen to anything you say.

I can see how an average consumer would fall for "5nm". But this is targeted at engineers ...

This is similar to all the disk space advertising and perpetual need to explain to friends why their disk isn't actually 500MB -> 2TB over the years.

If I look at HDD sizes and CPU "performance numbers", it doesn't surprise me that 5nm doesn't mean the actual transistor size.

Why not it's what computer power supply have done for decades.

1500W PSU!!! But you'll never know how we came up with that figure!

Outside of absolute no-name crap I haven't seen much of fake numbers on PSUs?

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