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Comment by jcfrei | Hacker News Reader

Does superconductivity remove or reduce the limit on die size?

Can't imagine why it would, but the lack of heat makes a 3D cpu much more feasible. So you could take 20 die, make 20 layers, and get radically more transistors per volume.

Seems like it would be much harder to keep a stacked CPU superconducting as heat dissipation would be more difficult.

Could a design with gaps between layers, but still connected as one not mitigate that though?.

Presumably 80x less power including cooling means more than 80x less power not including cooling.

I'd think that should be enough to get quite a few layers, sure maybe some minimal space between layers for cooling, but radically less than the non-superconducting designs.

Maybe I'm misunderstanding but since this 3D CPU would be superconducting, it would conduct electricity without resistance and therefore not generate any heat while in use.

Maybe there are parts which are not superconducting? Like impurities in the material. So even though the generated heat is like 0.01% of the original, some heat is still generated.

The adiabatic (reversible) computations themselves would be zero-loss, but in order to actually read the result of your computation you need to waste heat.

If you went a bit colder you could use superfluid helium and laser cut microchannels through the whole die. You would need to cool it to 2K and every degree at that temp is a fight but once past the transition point it becomes a remarkable thermal conductor and loses all viscosity. It seeps through tiny pores in porcelain like it's a sponge.

Solid idea, but the same thing that makes it work is what makes it impractical. Helium is almost impossible to contain long term, and would have to be replenished regularly.

I'm making a naive guess here. No, superconducting transistors are probably harder to create than non super conducting transistors so the limits on die size from defects are even more pronounced and superconducting doesn't change the speed of light for electrons on the chip so it doesn't change the timing issues arising from large dies.

The limits on die size for the competitive consumer chip market are nothing like that of the B2B market. Largest chip ever made was over 40,000 mm^2 [1] compared to Intel's 10900K at ~205 mm^2. In production mainframe chips like IBM's Z15s are on the order of 700mm^2. The fab process has a lot of levers so very low defect rates are possible but not at the scale of a consumer CPU.

[1] https://techcrunch.com/2019/08/19/the-five-technical-challen...

Edit: I assume a supercoducting microprocessor would use a strategy similar to the AI monolith in [1]. Just fuse off and route around errors on a contiguous wafer and distribute the computation to exploit the dark zones for heat dissipation.

If implemented using switches based on the Josephson effect like here, then no.

The thickness of the required insulating barrier presents a hard lower limit to the structure size.

The actual value of that limit depends on the material used and the particular implementation of the Josephson junction, of which there seems to be quite a few.

So the limit depends on how thin the barrier can be made.

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