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Comment by messe | Hacker News Reader

From sysctl -a on my M1:

    hw.cachelinesize: 128
    hw.l1icachesize: 131072
    hw.l1dcachesize: 65536
    hw.l2cachesize: 4194304

EDIT: also, when run under Rosetta hw.cachelinesize is halved:

    hw.cachelinesize: 64
    hw.l1icachesize: 131072
    hw.l1dcachesize: 65536
    hw.l2cachesize: 4194304

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Compared to the i9-9880H in my 16" MacBook Pro:

    hw.cachelinesize: 64
    hw.l1icachesize: 32768
    hw.l1dcachesize: 32768
    hw.l2cachesize: 262144
    hw.l3cachesize: 16777216

The M1 doubles the line size, doubles the L1 data cache (i.e. same number of lines), quadruples the L1 instruction cache (i.e. double the lines), and has a 16x larger L2 cache, but no L3 cache.

M1 cache lines are double of what is commonly used by Intel, AMD and other ARM microarchtectures use. That's significant difference.

sysctl on m1 contains the cache sizes for the little cores (since those are CPUs 0-3)

big cores (CPU4-7) have 192KB L1I and 128KB L1D.

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