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Comment by nabla9 | Hacker News Reader

What is the cache line size and page table size in M1?

    sysconf(_SC_PAGESIZE); /* posix */

Can you get direct processor information like LEVEL1_ICACHE_ASSOC and LEVEL1_ICACHE_LINESIZE from the M1??

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`getconf PAGESIZE` returns 16384 on the base M1 MacBook Air.

The L1 cache values aren't there. The macOS `getconf` doesn't support -a (listing all variables), so they may just be under a different name.

edit: see replies for `sysctl -a` output

Is it possibly exposed via sysctl, which does support a flag to list all variables?

From sysctl -a on my M1:

    hw.cachelinesize: 128
    hw.l1icachesize: 131072
    hw.l1dcachesize: 65536
    hw.l2cachesize: 4194304

EDIT: also, when run under Rosetta hw.cachelinesize is halved:

    hw.cachelinesize: 64
    hw.l1icachesize: 131072
    hw.l1dcachesize: 65536
    hw.l2cachesize: 4194304

M1 cache lines are double of what is commonly used by Intel, AMD and other ARM microarchtectures use. That's significant difference.

Compared to the i9-9880H in my 16" MacBook Pro:

    hw.cachelinesize: 64
    hw.l1icachesize: 32768
    hw.l1dcachesize: 32768
    hw.l2cachesize: 262144
    hw.l3cachesize: 16777216

The M1 doubles the line size, doubles the L1 data cache (i.e. same number of lines), quadruples the L1 instruction cache (i.e. double the lines), and has a 16x larger L2 cache, but no L3 cache.

sysctl on m1 contains the cache sizes for the little cores (since those are CPUs 0-3)

big cores (CPU4-7) have 192KB L1I and 128KB L1D.

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