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Comment by choletentent | Hacker News Reader

I am glad they are using System Verilog. It is hard for me to understand why SiFive chose Chisel as RTL language. I think that quietly slows down the RISC-V adoption. I honestly tried to understand the advantages of Chisel, but I can not see any. There is an answer on Stack Overflow regarding Chisel benefits, it is just embarrassing [1].

[1] https://stackoverflow.com/questions/53007782/what-benefits-d...

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I wrote a long blog post about the VexRiscv RISC-V CPU and how its design methodology is radically different than traditional RTL languages.

The VexRiscv is written in SpinalHDL, which is a close relative of Chisel.

The advantage of SpinalHDL/Chisel is that it supports plug and play configurability that’s impossible with languages like SystemVerilog or VHDL.

You can read about it here: https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CP...

That said: there must be at least 50 open source RISC-V cores out there, and only a small fraction is written in Chisel. I don’t see how the use of Chisel has held back RISC-V in any meaningful way.

I really want to bonk on the head anyone praising SystemVerilog. This collective undertaking of corrupt commitee members locked us in to this horrible language and these grossly outdated tools, forever. There is not a slightest bit of good in that languge, neither for design nor for verification.

That's a big call. Care to support it?

There are tons of people using System Verilog for RISC-V. The majority of work done is with System Verilog and not Chisel. Having lots of cores in both Chisel, System Verilog and many other languages (VHDL,BlueSpec and so on) is a huge benfit for RISC-V

SiFive values programmability above everything and for that Chisel is pretty clearly an advantage.

Please note I am software dev, not a hardware guy, and I just got my first FPGA during holidays, and am just beginning to play with it.

> There is an answer on Stack Overflow regarding Chisel benefits, it is just embarrassing [1].

I don't understand what is embarrassing about the answer ? As a software guy above answer make sense. Some problems you want to use C (or similar) for and some problems you want to use scripting language for, and then again sometimes the right tool is erlang, rust or go-lang ...

But like I said, that's my software guy perspective, so I am wondering what I missed?

I just read the answer as well. It's not "embarrassing", but it basically doesn't answer the question. Instead, it argues that the question is equivalent to asking what's the point of Python vs. C.

So in the end, the answer doesn't provide any specific answer regarding SystemVerilog and Chisel. All I found is one mention of negotiating parameters, which Verilog doesn't do. I would have loved to hear a lot more about examples of what Chisel makes more convenient than SystemVerilog.

SiFive really didn’t choose chisel as much as created it. It’s basically a company created by Krste and some former graduate students.

I like chisel as a concept but the learning curve is too high: Scala is kind of a mess and when you add a custom DSL + lots of functional programming on top a different hardware design methodology, it becomes overwhelming to your typical ce/ee, who probably doesn’t have that exposure. I simply ran out of time to learn it properly.

It also a second class citizen when it comes to rtl tools. The verification engineers have to work with the generated verilog and it looks like a nightmare. There was some improvements recently but the engineers knowledgeable enough to work on this stuff seem pretty bandwidth constrained.

The biggest headwind to chisel is the breadth of knowledge required to work and improve it IMO.

I’m really hoping that pymtl gets a firrtl backend soon. Python has a pretty decent record for building DSLs.

I don't have any relation to Chisel but the answer basically said you can take advantage of the Scala ecosystem to create hardware designs. That includes the ability to write arbitrary Scala to generate parameterized designs and the ability to create chisel libraries and publishing them as if they were regular Scala libraries. If you don't like Scala (like me) none of this matters for a "from scratch" design.

Google built one of their TPUs in Chisel [1].

TL;DW: Chisel is beautiful/fun to write in, with a definite productivity bonus, but has a pretty large learning curve and had a much greater verification cost, partly because it's an HLS (most have that problem) and also lack of any tooling. Both of those costs are gradually being reduced (though in my opinion, not enough to not make verification a PITA).

[1] https://www.youtube.com/watch?v=x85342Cny8c

What is an HLS?

High Level Synthesis

Facts:

Chisel is NOT HLS at all. Chisel is one of many languages that generates HDL, that is, you describe code to built a circuit whereas in eg. Verilog you just describe the circuit (Verilog has a limited ability to do dynamically with generate statements).

An HLS is one that raise the abstraction. Almost all of them today allows you to write "lightly" annotated C[++] that gets translated into a circuit. Almost universally, the timing relationship isn't explicit at all.

Opinions:

All existing HDLs and HLSes are terrible and there's fertile ground for creating something to really advance the art. Personally I'm looking for something that is more productive that HDLs, but with more control than an HLS. Some promising examples: Handle C, Google's XLS (assuming promised development), and Silice.

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