RISC-V Vector Instructions vs. ARM and x86 SIMD

Maybe the vector instructions are interruptable like the "increment and repeat" instructions on the Z80 (e.g. LDIR)? LDIR could copy a block of memory up to 64 KBytes (which would take nearly 1.4 million cycles), but even though it looked and behaved like a single instruction to the programmer it was actually looping over itself until the transfer has completed by simply not incrementing the program counter until register BC (used as byte counter) is zero. The downside is that each copied byte required to fetch and decode the whole 2-byte instruction again (costing 21 cycles per copied byte), but the upside is that those increment-and-repeat instructions are interruptible, since they are actually a regular loop of the same 21-cycle instruction over and over again.

My understanding of these RISC-V vector instructions is that they're limited to a vector register, which probably won't be too big, perhaps 512-bits or so. Compared to the cost of a context switch, the cost of finishing the current instruction should be negligible.