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Comment by gwf | Hacker News Reader

Looking at the documentation, it reads as if the architecture has a proper clock that synchronizes all computation. Furthermore, an emulator would naturally have a global notion of time, synchronously updating all internal states in a linear sweep.

However, in hardware this model could be made clockless / asynchronous, such that computations go as fast as they can. The extra state of "unknown" can be interpreted as "not all required inputs are ready yet". Some care would be needed to buffer loops in a recurrent circuit, but that's about the only extra complication.

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> However, in hardware this model could be made clockless / asynchronous

I know you didn't imply otherwise, but it's worth pointing out that ternary logic is by no means required for asynchronous hardware design. The same effect is possible with dual rail channels using two wires per bit, or even fewer on average using Sperner codes and the like.

> computations go as fast as they can

Although asynchronous circuits might not have to wait for a clock, they do have to wait for handshake completion detection in various forms. It's more like a trade-off than a free lunch.

Indeed the two binary rails approach corresponds to a logic as well, namely Belnap's A4: https://en.m.wikipedia.org/wiki/Four-valued_logic

Yep, which is exactly what I did here:

https://core.ac.uk/download/pdf/82751815.pdf

This project appears to be loosely inspired by the Setun series of computers made in the Soviet Union. I can't find any information in English about those being asynchronous designs. The choice of ternary appears to have been made to avoid the signed/unsigned distinction.

I don’t think it will work with trinary numbers though, as in his design “unknown” is treated as “zero”.

So if there is an adder which outputs “0”, there is bo way to tell if the computation was done and result was zero, or if it is still in progress.

Agreed, not with this particular design. However, you can absolutely do this just ternary numbers. You loose the ability to encode 3^n states (and are stuck w/ just 2^n), but the middle state can then be repurposed to indicate if the computation is complete (or not) as of yet.

I basically used this sort of design in a dual-rail logic framework which had 4 line-states per "data" line pair, two of which were real data bits, a third indicated unknown vs. unknown, and the fourth was unused.

See https://core.ac.uk/download/pdf/82751815.pdf, but beware that even though it doesn't look at all like ternary numbers in use, it absolute is.

What applications would be best suited to use this? I can't think of anything apart from scientific work that would benefit from such a specialized design.

None. The point of the paper was the proof technique, which was later extended to include a large family of constrained motion planning problems (i.e., problems that previously were of an unknown computational complexity could be easily mapped to the framework, thereby proving that they were PSPACE-complete).

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