The RISC V position is that compressed instructions with macro ops fusion can solve this issue:

  https://erik-engheim.medium.com/the-genius-of-risc-v-microprocessors-b19d735abaa6

We'll see in practice as more powerful RISC V cores are developed and used. For a new architecture like this it's normal to start with deeply embedded (and relatively low power) cores, and then move up the food chain. It takes time to build an ecosystem.

Currently the ISA is minimalist but I assume that at the high end some extensions still in development will eventually become expected, like bit operations or the vector extension.