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I have been trying to explain to people that having the DRAM chips physically next to the SOC on the package does not actually meaningfully improve memory latency.

I get that people on this site are excited, but please be excited about the right things.

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People seem to have dramatically missed the point here; it's almost certainly done for power reasons.

And also for silicon budget, probably: short distances require small interface transistors and thin wires compared to massive distances like 5cm.

The chip area can be re-used for compute-sized transistors and wires (much, much smaller than interface transistors and wires, so there can be many more of them).

Yeah, speed of PCB transmission is ~8 inches (~20cm) per nanosecond. Which is about 2/3 of the classic "light-nanosecond", which is roughly a foot.

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