This helps alleviate problems stemming from the curse of dimensionality, such as the need for data sets that scale exponentially with the number of features. This is precisely an area where x86 architecture and CISC ISA will out rank the RISC-V ISA of M1's.
But perhaps, I don't know what I am talking about. Someone with more knowledge, please chime in.
[1] https://web.archive.org/web/20140311005243/http://machinelea...
[2] https://www.researchgate.net/publication/228845263_An_Empiri...
If naive bayes is really embarassingly parallel, SIMD+lots of cores help here of course. It is also probably highly optimized code that doesn't rely so significantly on OoO capabilities and can take advantage of the higher clock rate.
Even Itanium was very good at numerical code.
https://medium.com/swlh/what-does-risc-and-cisc-mean-in-2020...
confused.