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Comment by aey | Hacker News Reader

Because of the 12MB L2 cache as the point of unification. 865 snapdragon has a 4mb L3. Same as my recent intel MacBook.

Apple can use at least as much more die as amd/qcom/intel’s profit margin.

Also being on TSMC5 on top of significant micro architecture improvements ; ~630 instruction deep ROB, ability to queue ~150 outstanding load instruction and ~100 outstanding stores and huge TLBs which reduces swapping the anandtech article does a great job going into explaining this.

All that helps, but if you look at the die you are going to see a massive 12MB L2 with a bunch of routing to all the L1s. That’s where the majority of the cost is going vs any other chip.

If cache size was the answer then Intel would have already stuck more on their CPUs, and AMD's 32MB on Zen3 would be carrying far more weight against the M1 than it is.

Bigger caches mean higher latency caches, it's not strictly a matter of bigger is better.

It’s an L2, amd zen has 2x16mb L3s, with a wacky point of unification. L3 is muuuuch slower than L2.

Apple’s L2 is huge and is the PoU for all the cores. I wouldn’t be surprised if it has direct routing to all the L1s since they are so small. 5nm doesn’t hurt.

> amd zen has 2x16mb L3s

Zen 3 is not, it's a single 32MB L3 per chiplet.

> L3 is muuuuch slower than L2.

"L2" and "L3" are just how many layers away from the CPU it is, it's not an intrinsic "type" of cache. The speed is a function of the size.

Intel probably should have dropped their profit margin just to prevent this embarrassment. This is the foot in the door. Or through the door.

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