MIT 6.004 L14: Implementing RISC-V Processor in Hardware | Hacker News Reader

MIT 6.004 L14: Implementing RISC-V Processor in Hardware

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113 pointshomarp22 comments

Not sure why link a tweet, what you're looking for is [1]. While we're at it, take a look at MIT's other courses at [2]. They are amazing. I wish all schools'd put up their classes online for free.

[1] https://ocw.mit.edu/courses/electrical-engineering-and-compu...

[2] https://ocw.mit.edu/courses/

The linked tweet is to a slightly more recent rendition of the course (spring 2020 I think). It doesn't appear to be linked from the ocw.mit.edu web page yet. I don't see RISC-V in the syllabus of your linked 2017 version, but I may have missed it.

I thought I went to the wrong link as well, the link in OP's comment links to a data structures course? A copy-paste mistake perhaps?

The link from the original Twitter post seems to load to the right RISC course from Fall 2020: https://6004.mit.edu/web/fall20/resources/sp20

> I wish all schools'd put up their classes online for free.

By the way you can thank Hal Abelson* (also known for SCIP, patronage of the FSF, and many other things) for making this happen almost 20 years ago. And “making it happen” was more than just sticking some videos online — which wasn’t even the first thing — but aiming to put all the course material online and encouraging others to use it for their own courses.

It’s particularly striking to me that it was MIT that did this as the institute is notorious for feeling and acting like it considers the educational part of its mission as an annoying distraction.

* Don’t get me wrong — many people were involved. But Hal was IMHO the most instrumental.

>more than just sticking some videos online — which wasn’t even the first thing — but aiming to put all the course material online and encouraging others to use it for their own courses.

Actually putting video (and, for the most part, audio) wasn't even really all that practical when OCW was created. One also suspects that it was an easier sell that OCW was for educators rather than being, in any way, an alternative to taking the courses in-person. OCW was a great innovation though even if it wasn't what a lot of would-be students were looking for. Which ended up being MOOCs that were more directly consumable although still mostly flawed in various ways.

because it had a brief description, mentions the RISC-V part that I'm interested in, with a direct link to video and slides.

For me probably the coolest thing about RISC-V is it has version with a simple enough architecture that students can code it in a quarter, and it's also in the zeitgeist in a way MIPS never was. It seems like we've been doing toy MIPS implementations for years [1] but they just never captured the imagination in the same way. RISC-V feels almost like the cpu architect's MINIX. :)

[1] Just one random example http://pages.hmc.edu/harris/cmosvlsi/4e/index.html

>"For me probably the coolest thing about RISC-V is it has version with a simple enough architecture that students can code it in a quarter"

What do you mean by "version" here? How does it add to its accessibility?

I'm curious about your or anyone else's opinion of that "CMSO VLSI Design" text book you linked to. It's quite expensive and I haven't been able to bring myself to buy it. Would you recommend it?

This class’s version of RISC-V only implements of subset of all the possible instructions (which of course is totally appropriate) and it’s missing modern concepts (like out of order execution) which are also out of scope for an introductory class. One of the lectures describes basic logic gates so one doesn’t go from that to reorder buffers in a single quarter.

I think the Weste text book is an excellent introduction to the reality of (mostly) modern digital VLSI design. My only gripe is it’s weak on analog, which is my forte. For An introduction to the reality of that I think Baker’s text at cmosedu.com is better.

Basically, if you have interest in the subject buying a used copy of Weste is not likely to disappoint. Or perhaps see if your local library can snag a copy before you buy.

Oh I see. Yes it's a modular design. That's one of the most fascinating elements of the CPU. I wasn't familiar with the version terminology to denote features. Thanks. Also thank for the the feedback on the Weste book. I will try to find a used copy.

> familiar with the version terminology

That's probably because I was using the wrong word. I should've said "variant".

> What do you mean by "version" here? How does it add to its accessibility?

The base variant of RISC-V (RV32/64I) is extremely bare bones.

Even instructions for integer multiplication/division and floating points, atomics, ... are all added by extensions.

See https://en.wikichip.org/wiki/risc-v/standard_extensions

Because MIPS was proprietary and it could never be more then a toy.

IIRC MIPS 4000 had source available and could be used freely.

Probably a sanguine moment to mention that the selfie project appears to have migrated from MIPS to RISC-V:

https://selfie.cs.uni-salzburg.at/

> An educational software system of a tiny self-compiling C compiler, a tiny self-executing RISC-V emulator, and a tiny self-hosting RISC-V hypervisor.

> Selfie is a project of the Computational Systems Group at the Department of Computer Sciences of the University of Salzburg in Austria.

> The Selfie Project provides an educational platform for teaching undergraduate and graduate students the design and implementation of programming languages and runtime systems. The focus is on the construction of compilers, libraries, operating systems, and even virtual machine monitors. The common theme is to identify and resolve self-reference in systems code which is seen as the key challenge when teaching systems engineering, hence the name.

(No affiliation, I just like it.)

Wow this is a very cool project! Do you know of any available video lecture from anyone teaching the curriculum? Unfortunately the name of the project makes searching a little difficult.

Cheers! I know what you mean about the name. I don't know of any videos offhand but you could just drop them an email and ask?

I guess it all depends on what side you're coming from. When I was in school, I studied MIPS from the perspective of a compiler writer who's only casually interested in hardware design. Having learned a couple of CISC designs beforehand, I found MIPS to be absolutely genius in comparison. I wasn't interested so much in implementing a MIPS processor, just coding for it.

This is really cool - I hope people will start offering companion courses: "Verifying a RISC-V processor". If you've done both, it's a real multiplier for your understanding of CPUs and hardware generally.

Not something I know a lot about, but modern CPUs tend to be too complex for current formal verification techniques, and often have bugs, no?

e.g. https://www.zdnet.com/article/amd-owns-up-to-cpu-bug/ , https://www.extremetech.com/computing/254750-amd-replaces-ry...

Is there any website to get duly updated on this super awesome courses? The OCW MIT site is not even reflecting that this edition of the course was released.

Similar example to this one... latest publishing of CS193P (iOS Development) was released a few months back, its awesome, but no traces of it on iTunes or other sites, found it on Twitter, so I have the feeling I am missing many of these..

This will be an unpopular opinion in some quarters, but I'm ready for RISC-VI. Or -6.

RISC-V is pretty close, so work on verifying -V should mostly carry over to -6. A MIPS engineer posted a list, recently, of errata that mostly would not be hard to fix, such as (IIRC) having separate opcodes for call and return so the microarchitecture can optimize them independently.

I would add making the ABI bool true value ~0 instead of 1; and a POPCNT instruction in the base set, not dependent on a big "bitmanip" extension package.

The extensions infrastructure is itself a problem, illustrated by the last point. Often, certain key parts of an extension are disproportionately useful, but you don't get the sink without a whole kitchen attached.

We probably won't get a new mainstream architecture for decades, so it is worth getting this one right before too much is committed. It would be disruptive to try to fix -V, but -6 work can go on in parallel.

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