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I have read somewhere that there is no benefit of making multiple layers of transistors per chip because you get to thermal limits pretty quick.

We barely can keep 1 layer whithin operating temperature.

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Generally caches, especially those using the full 8 transistors per cell instead of those trying to get by with 6, don't use all that much power. One obvious idea is to design a chip such that the hot logic layers are on top, right next to the heat sync, and the logic layers are underneath. 3D topology means that everything can effectively be closer together for lower latency and lower information transport energy but you can make the caches bigger at the same time.

For true 3D chips that are more cube-like people talk about putting liquid cooling channels into the structure but that would be a technology for quite a ways off.

Yes and no. You do run into thermal limits, but you can control how much power you draw by adjusting voltage and clock speed. Somethings are more "transistor" hungry than "cycle" hungry.

That said, I expect the early uses might be in mixed mode (linear and digital devices in the same package) and things that benefit from a huge cache or pre-programmed ROM.

There are also things like diamond substrates that improve the thermal transfer characteristics as well which helps you to draw more heat from the package than just silicon. This was a feature of "silicon on sapphire" processes and perhaps we will see some "silicon on diamond" parts.

Under some constraints [1] [2] if you halve the frequency and double the number of execution units, the overall power consumption drops.

Therefore, you could gain performance or reduce power by stacking layers of silicon.

This is also true for things like power LEDs; within a certain range of their operating curve (current vs. output) you can reduce current by X% and lose less than X% of output. Put down two LEDs, then, and you get more output at the same current.

[1] architectures that scale efficiently to more execution units, like GPUs

[2] you're in a suitable region of the frequency-power curve

Yes, the last 10 percent increase in clock speed causes a 30 percent increase in power, or something like that. If you care about total performance instead of single thread it's probably better to add more cores.

3D allows you place circuits closer together reducing latency, and to build more efficient layouts.

Circuit layout in 3D is O(n), vs np-complete in 2d.

I've always wondered why advances in 3D chips haven't taken advantage of nano-fluidics. One radical new chip design could be very micron-sized coolant pipes for wicking away heat. The "coolant" could perhaps be gallium for rapid heat transfer. Micro-valves could open/close as parts of the chip draw more power, pumping more fluid through them, and cooling them faster.

Every problem has a solution, we must be creative enough to discover & build it.

Microfluidics is one of the most complex fields to commercialize a product in, and is littered with dead startups. The short answer is that the scale change changes the behavior of everything - pumps and flow just plain don't work the way they do at larger scales, and the forces created by surface tension and hydrophillicity become large relative to the strength of the mechanical parts.

What's the breakthrough needed to make chips like these a reality?

As in any cutting-edge technology: enough willpower and finance to explore the design space until a design with sufficient potential is found and its technical challenges overcome. Academia often has already explored the design space. The industry then tries to commercialize one of these approaches. Often, they turn out to be a dud: the challenges are too large, or they are solvable but the technology is ultimately impractical for some reason, or they are a dead end and thus won't be relevant for long enough to build a company on it. And then there are various non-technological human failure modes that can befall a company...

Nanoscale fluidics are much more efficient at transferring heat or mass. The issue is that we have just started developing an understanding of the field, so our usual understanding of those concepts have to be developed from scratch. As you mentioned, the forces become large enough, and some variables can't just be ignored. But in my experience (working with microscale perfusion reactor arrays), they actually deliver much more and reliably compared to a conventional system.

To get a 10* speed up you would need 10* the power. Your 100w cpu would become 1kw! Its not a long term winning strategy to chase after better thermal dissipation. When we have 2d devices that running as fast as they can go and drawing 1w, then it's time to go vertical.

One could imagine to use 1 layer while the other is cooling, then switching when the current layer get too hot? But I guess the heat from 1 active layer would quickly propagate to the whole chip.

Or maybe using more transistors allow to run them at a lower power to complete the same work, which reduces the dissipated energy ?

With a 2-d chip, you can't do much better than a big-old heat sink, and circulating a fluid. For 3-d structures, I wonder if actively moving heat to the outside with Peltier junctions would help.

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