Advanced System-on-Chip Design Lecture Notes
iis-people.ee.ethz.ch
iis-people.ee.ethz.ch
1 Basic Processor & Memory hierarchy
2 Advanced Out-of-Order Processor
3 Data-parallel processors
4 Micro-controller introduction
5 Multicore
6 RISC-V core
7 Advanced Multicore
8 Multicore programming
9 Graphics Processing Unit (GPU)
10 Heterogeneous SoC
11 GPU Programming
12 Application-Specific Instruction-Set Processor (ASIP)
13 PULP: Parallel Ultra-Low-Power Computing
14 Architecture in the Future - Wrap-up
[1] https://iis-people.ee.ethz.ch/~gmichi/asocd/classinfo/ASoCD_...> wget -m -p -E -k -K -np https://iis-people.ee.ethz.ch/\~gmichi/
https://github.com/fabianschuiki/llhd
p/s: It seems that Lecture 7 slide is missing, though.
However, there is one thing is regrettable to me in lectures that talks about the micro-architecture of superscalar processors: they never talk about the register bank micro-architecture. The focus is always on the micro-architecture of the compute units.
Knowing that the wire area of a conventional register bank grows by the square of the number of read/write ports, and that superscalar processors require an increasing number of read/write ports, the micro-architecture of the register bank quickly becomes critical with the number of issue.
But there is very little information on the right micro-architectural strategy in this regard. There is some information on GPU register banks, but very little about modern CPU designs.