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Comment by mschuster91 | Hacker News Reader

> The same HDL that can be configured into an FPGA can be used to make chips.

Not exactly, you'll likely have to replace FPGA HW blocks for "hard IP" such as I/O (especially high speed interfaces such as HDMI/DP, MII, but also RAM controllers), power and clock management...

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I'm also worried about this, which is part of the reason why the Precursor design avoids using hard IP blocks like RAM and USB controllers. It does limit the performance of the system (we have a simple async RAM interface and full-speed USB only), but the explicit priority is transparency over performance.

The main attack surfaces to worry about when translating this design to an IC are the RAM, boundary scan and eFuse macros, and perhaps slightly less so the PLL and ADC blocks. While these are not trivial blocks to be worried about, there may be things we can do at a design level to complicate attempts to bake back doors into these blocks, and we're investigating methods to verify their correct in-silicon construction non-destructively.

What about the metrology cutouts you have to leave in every 2mm by 2mm region on 28nm and lower processes? I hear the interval is even smaller on 14nm/7nm.

I always thought those were only half for process control and half to force you to leave a blank spot on your mask where they could pattern in nasty additional circuitry on a few wafers.

Edit: TSMC calls this the "Dummy TCD macro". If you have the 28nm design rule book T-N28-CL-DR-002 version 1.3 it's Section 6.3.3 "Dummy TCD Design Insertion Guideline" (if you don't have the design rule book then no, I can't send it to you, please don't ask). The TCD macro is a black box -- nobody outside TSMC gets to see what's in it. You have to leave a 9um*3.5um empty region on all layers in every 2mm by 2mm region of your maskset.

Now that Multi Layer Maskset (MLM) is widespread every fab has the ability to "blade off" regions of a mask and expose a pattern from a different mask in that region (of course wafers processed this way are much much more expensive). The TCD macro rules force you to leave an empty hole in your design at regular intervals where this can be done without breaking your chip.

> I always thought those were only half for process control and half to force you to leave a blank spot on your mask where they could pattern in nasty additional circuitry on a few wafers.

Holy fucking hell. So that is what the comment in https://news.ycombinator.com/item?id=24919073 might have alluded to?

Is there any way to take a random TSMC-fabbed chip and inspect this region, or are the feature sizes too small?

> So that is what the comment in https://news.ycombinator.com/item?id=24919073 might have alluded to?

Oh, no, it gets much worse. Take the blue pill, turn back from this rabbit-hole now; Here Be Dragons.

The amount of FUD that goes on HN related to hardware never ceases to amaze me.

Sometimes I find myself double checking if I am really on HN and not on Facebook.

Of course "the same HDL" is a reductive statement, since components like high-speed IO, or even clock gates are not easily portable between FPGA vendors or foundries. But the user-land Verilog/VHDL code that describes how your custom thing "works" is generally portable.

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