And we have pretty great open source cpu & ram design tools. MAGIC is free. There's a lot of great tools fora lot of this.
What is not so great is all the un-core. And GPU, if you want that.
The SiFive boards were coming with TileLink[1] as the main way to talk to the core, for a while, I believe, which is a pretty low level cache-coherent fabric used no where else. There's decent off the shelf to design a lot of the digital systems here. But I don't know what resources if any are available to help you build a chip-to-chip interface, to expose the TileLink. And there's basically the world's tiniest market for things to plug in on the other end anyways.
When you buy an SoC, almost all embedded folk expect a bunch of semi-standard capabilities. I2C, I2S, DisplayPort, USB, Ethernet, &c are all common things you might want. While we can make a decent cpu now a days, afaik, we are still in very very very early days, very pre-implementation, for almost all of these. Thusfar almost everyone relies on buying closed IP to provide connectivity for the SoC they are making. It's quite likely to be the case as well for the new SiFive Unmatched board; I expect they bought someone's PCIe IP & integrated it.
We are starting to see more neat work with FPGA implementations of various protocols like USB3 & PCIe but these all rely on the FPGA having really good transceivers that tackle the PHYsical layers, do the dirty work. Building actual transistors to be receivers & transmitters into & out of the chip, that's where, atm, we are all but babes, it feels like.
$70K 20 WEEKS 100 SAMPLES
See also: https://theamphour.com/503-fabless-chip-design-with-mohammed...
Definitely older processes have much cheaper mask sets -- in part because there are just fewer metal layers, and fewer & cheaper masks required to image the transistors when the wavelength of light used (193nm) is close to the line width of the devices themselves.
https://mamot.fr/@pluralistic/105183378364921755
I really think this is the killer point of it all. The cores are the easy part. The digital part. Are we making headway anywhere else? Eh, yes, a tiny bit? Barely?
The same HDL that can be configured into an FPGA can be used to make chips.
But we won't get there without the FPGA step. Chips aren't designed directly anymore. The sort of complexity we need these days means it's impossible to get right on the first try, and mistakes are very costly with ASICs.
Not exactly, you'll likely have to replace FPGA HW blocks for "hard IP" such as I/O (especially high speed interfaces such as HDMI/DP, MII, but also RAM controllers), power and clock management...
The main attack surfaces to worry about when translating this design to an IC are the RAM, boundary scan and eFuse macros, and perhaps slightly less so the PLL and ADC blocks. While these are not trivial blocks to be worried about, there may be things we can do at a design level to complicate attempts to bake back doors into these blocks, and we're investigating methods to verify their correct in-silicon construction non-destructively.
I always thought those were only half for process control and half to force you to leave a blank spot on your mask where they could pattern in nasty additional circuitry on a few wafers.
Edit: TSMC calls this the "Dummy TCD macro". If you have the 28nm design rule book T-N28-CL-DR-002 version 1.3 it's Section 6.3.3 "Dummy TCD Design Insertion Guideline" (if you don't have the design rule book then no, I can't send it to you, please don't ask). The TCD macro is a black box -- nobody outside TSMC gets to see what's in it. You have to leave a 9um*3.5um empty region on all layers in every 2mm by 2mm region of your maskset.
Now that Multi Layer Maskset (MLM) is widespread every fab has the ability to "blade off" regions of a mask and expose a pattern from a different mask in that region (of course wafers processed this way are much much more expensive). The TCD macro rules force you to leave an empty hole in your design at regular intervals where this can be done without breaking your chip.
Holy fucking hell. So that is what the comment in https://news.ycombinator.com/item?id=24919073 might have alluded to?
Is there any way to take a random TSMC-fabbed chip and inspect this region, or are the feature sizes too small?
Oh, no, it gets much worse. Take the blue pill, turn back from this rabbit-hole now; Here Be Dragons.
Sometimes I find myself double checking if I am really on HN and not on Facebook.
The promised "November run" did not materialize, and there's nothing solid on rescheduling it.
Kind of a let-down.
From the article: 1M US-$ at least for the masks plus a boatload of other upfront investment. If you're for bleeding-edge tech like new fab processes, orders of magnitude more.